54F322 Datasheet



Features, Applications
54F 74F322 Octal Serial Parallel Register with Sign Extend

The an 8-bit shift register with provision for either serial or parallel loading and with TRI-STATE parallel outputs plus a bi-state serial output Parallel data inputs and parallel outputs are multiplexed to minimize pin count State changes are initiated by the rising edge of the clock Four synchronous modes of operation are possible hold (store) shift right with serial entry shift right with sign extend and parallel load An asynchronous Master Reset (MR) input overrides clocked operation and clears the register


Multiplexed parallel I O ports Separate serial input and output Sign extend function TRI-STATE outputs for bus applications

Package Description (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C

Note 1 Devices also available in 13 reel Use suffix e SJX

Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB

TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation 9516 RRD-B30M105 Printed S A

Register Enable Input (Active LOW) 6 mA Serial (HIGH) or Parallel (LOW) Mode Control Input 6 mA Sign Extend Input (Active LOW) 8 mA Serial Data Select Input 2 mA Serial Data Inputs 6 mA Clock Pulse Input (Active Rising Edge) 6 mA Asynchronous Master Reset Input (Active LOW) 6 mA TRI-STATE Output Enable Input (Active LOW) 20 mA Bi-State Serial Output 33 3 Multiplexed Parallel Data Inputs 65 mA TRI-STATE Parallel Data Outputs mA (20 mA)

The 'F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations A LOW signal on RE enables shifting or parallel loading while a HIGH signal enables the hold mode A HIGH signal S P enables shift right while a LOW signal disables the TRI-STATE output buffers and enables parallel loading In the shift right mode a HIGH signal on SE enables serial entry from either D1 as determined by the S input A LOW signal on SE enables shift right but Q7 reloads its contents thus performing the sign extend function required for the 'F384 Twos Complement Multiplier A HIGH signal on OE disables the TRI-STATE output buffers regardless of the other control inputs In this condition the shifting and loading operations can still be performed

Mode Select Table Mode MR Clear Parallel Load Shift Right Sign Extend Hold RE Inputs O6 NC Outputs NC Q0

When the OE input is HIGH all I On terminals are at the high impedance state sequential operation or clearing of the register is not affected Note �I0 e The level of the steady-state input at the respective I O terminal is loaded into the flip-flop while the flip-flop outputs (except Q0) are isolated from the I O terminal Note D1 e The level of the steady-state inputs to the serial multiplexer input Note �O0 e The level of the respective Qn flip-flop prior to the last Clock LOW-to-HIGH transition H e HIGH Voltage Level L e LOW Voltage Level Z e High Impedance Output State L e LOW-to-HIGH Transition e No Change



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