Homedatasheet54F651

54F651 Datasheet

Bus Oriented Circuits
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Description

Features, Applications

These devices consist of bus transceiver circuits with D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers Data on the or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level Output Enable pins (OEAB OEBA) are provided to control the transceiver function

Features

Independent registers for A and B buses Multiplexed real-time and stored data Choice of non-inverting and inverting data paths 'F651 inverting 'F652 non-inverting Guaranteed 4000V minimum ESD protection

Package Description (0 300 Wide) Molded Dual-In-Line (0 300 Wide) Ceramic Dual-In-Line (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carrier Type (0 300 Wide) Molded Dual-In-Line (0 300 Wide) Ceramic Dual-In-Line (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carrier Type C

54F651SDM (Note 2) 74F651SC (Note 1) 54F651FM (Note 2) 54F651LM (Note 74F652SPC 54F652SDM (Note 2) 74F652SC (Note 1) 54F652FM (Note 2) 54F652LM (Note 2)

Note 1 Devices also available in 13 reel Use suffix e SCX

Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB

TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation

B7 A and B Inputs 6 mA TRI-STATE Outputs mA (48 mA) CPAB CPBA Clock Inputs 6 mA SAB SBA Select Inputs 6 mA OEAB OEBA Output Enable Inputs 6 mA

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays


Features

Parameters

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Manufacturer information

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