Homedatasheet54F823

54F823 Datasheet

Military/Aerospace->FAST
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Description

Features, Applications

The a 9-bit buffered register It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems The 'F823 is functionally and pin compatible with AMD's Am29823

Features
TRI-STATE outputs Clock Enable and Clear Direct replacement for AMD's Am29823

Package Description (0 300 Wide) Molded Dual-In-Line (0 300 Wide) Ceramic Dual-In-Line (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Chip Carrier Type C

Note 1 Devices also available in 13 reel Use suffix e SCX

Note 2 Military grade device with environmental and burn-in processing Use suffix e SDMQB FMQB and LMQB

TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation

Data Inputs Output Enable Input Clear Clock Input Clock Enable TRI-STATE Outputs

The 'F823 device consists of nine D-type edge-triggered flip-flops It has TRI-STATE true outputs and is organized in broadside pinning The buffered Clock (CP) and buffered Output Enable (OE) are common to all flip-flops The flipflops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition With the OE LOW the contents of the flipflops are available at the outputs When the OE is HIGH the outputs go to the high impedance state Operation of the OE input does not affect the state of the flip-flops In addition to the Clock and Output Enable pins the 'F823 has Clear (CLR) and Clock Enable (EN) pins When the CLR is LOW and the OE is LOW the outputs are LOW When CLR is HIGH data can be entered into the flipflops When EN is LOW data on the inputs is transferred to the outputs on the LOW to HIGH clock transition When the EN is HIGH the outputs do not change state regardless of the data or clock inputs transitions This device is ideal for parity bus interfacing in high performance systems

Function Table Inputs OE CLR EN CP Internal Q NC Output NC Hold Clear Load Data Available Data Available No Change in Data No Change in Data Function

L e LOW Voltage Level H e HIGH Voltage Level X e Immaterial Z e High Impedance L e LOW-to-HIGH Transition e No Change

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays


Features

Parameters

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Manufacturer information

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