|54FCT373 Octal Transparent Latch with TRI-STATE Outputs
54FCT373 Octal Transparent Latch with TRI-STATE � Outputs
The 'FCT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state.Features
TRI-STATE outputs for bus interfacing TTL input and output level compatible CMOS power consumption Output sink capability of 32 mA, source capability mA n Standard Microcircuit Drawing (SMD) 5962-8764401
Military 54FCT373FMQB 54FCT373LMQB Package Number E20A 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Package Description 20-Lead Ceramic Dual-In-Line
Description Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) TRI-STATE Latch OutputsTRI-STATE is a registered trademark of National Semiconductor Corporation.
The 'FCT373 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. LEH = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance State
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State +5.0 mAin the HIGH State Current Applied to Output in LOW State (Max)
Free Air Ambient Temperature Military Supply Voltage Military to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Symbol VIH VIL VCD VOH VOL IIH IIL IOZH IOZL IOS ICCQ ICC ICCT Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage 54FCT FCT240 Min 0.8 -1.2 Max Units �A mA Min Max VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN -18 mA IOH -300 uA IOH -12 mA IOL 300 �A IOL 32 mA VIN = 5.5V VIN = 0.0V VIN = 5.5V VIN = 0.0V VOUT = 0.0V VIN 0.2V or VIN = 5.3V VIN = 3.4V VIN 3.4V or VIN =GND, OE = GND, = 10Mhz, outputs open, one bit toggling, 50% duty cycle VIN 5.3V or VIN 0.2V,OE = GND, = 10Mhz, outputs open, one bit toggling, 50% duty cycle Outputs Open, OE = GND, one bit toggling, 50% duty Cycle
Input HIGH Current Input LOW Current High Impedance Output Current High Impedance Output Current Output Short-Circuit Current Power Supply Current Power Supply Current Total Power Supply Current