Homedatasheet54FCT573DMQB

54FCT573DMQB Datasheet

Octal D-type Latch With Tri-state Outputs
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Description

Features, Applications
54FCT573 Octal D-Type Latch with TRI-STATE Outputs
54FCT573 Octal D-Type Latch with TRI-STATE � Outputs

The is an octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. This device is functionally identical to the 'FCT373 but has different pinouts.

Features

n Inputs and outputs on opposite sides of package allow easy interface with microprocessors n Useful as input or output port for microprocessors n TTL input and output level compatible n CMOS power consumption n Functionally identical 'FCT373 n TRI-STATE outputs for bus interfacing n Output sink capability of 32 mA, source capability mA n Standard Microcircuit Drawing (SMD) 5962-8863901

Military 54FCT573FMQB 54FCT573LMQB Package Number E20A 20-Lead Ceramic Dual-In-Line 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Package Description

Description
Latch Enable Input (Active HIGH) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Latch Outputs
TRI-STATE is a registered trademark of National Semiconductor Corporation.

The 'FCT573 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. OE

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial O0 = Value stored from previous clock cycle

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output +5.0 mA

Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input to +5.5V (V/t) 50 mV/ns 20 mV/ns

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Quiescent Power Supply Current Quiescent Power Supply Current Dynamic ICC 54FCT VOL 54FCT IIH IIL IOZH IOZL IOS ICCQ ICC ICCD �A mA mA/ MHz Max 0- 5.5V Max V Min -1.2 FCT573 Typ Max Min Recognized HIGH Signal Recognized LOW Signal IIN -18 mA IOH -300 �A IOH -12 mA IOL 300 �A IOL 32 mA VIN = VCC VIN = 0.0V VOUT = 2.0V VOUT = 2.0V VOUT = 0.0V VIN 0.2V or VIN 5.3V, VCC = 3.4V, VCC = 5.5V Outputs Open, VCC = 5.5V, VIN 5.3V or VIN < 0.2V, One Bit Toggling, 50% Duty Cycle, OE = GND, LE = VCC Outputs Open, fCP = 10 MHz, VCC = 5.5V, VIN 5.3V or VIN < 0.2V, One Bit Toggling, 50% Duty Cycle, OE = GND, LE = VCC Units VCC Conditions


Features

Parameters

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Manufacturer information

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