54LS169DMQB Datasheet

Synchronous 4-bit Up/down Binary Counter


Features, Applications

This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting applications Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs all change at the same time when so instructed by the countenable inputs and internal gating This mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple clock) counters A buffered clock input triggers the four master-slave flip-flops on the rising edge of the clock waveform This counter is fully programmable that is the outputs may each be preset either high or low The load input circuitry allows loading with the carry-enable output of cascaded counters As loading is synchronous setting up a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse The carry look-ahead circuitry permits cascading counters for n-bit synchronous applications without additional gating Both count-enable inputs (P and T) must be low to count The direction of the count is determined by the level of the up down input When the input is high the counter counts up when low it counts down Input T is fed forward to enable the carry outputs The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the high portion of the QA output when counting up and approximately equal to the low portion of the QA output when counting down This low-level overflow carry pulse can be used to enable successively cascaded stages Transitions at the enable or T inputs are allowed regardless of the level of the clock input All inputs are diode clamped to minimize transmission-line effects thereby simplifying system design This counter features a fully independent clock circuit Changes at control inputs (enable P enable T load up down) which modify the operating mode have no effect until clocking occurs The function of the counter (whether enabled disabled loading or counting) will be dictated solely by the conditions meeting the stable setup and hold times


Fully synchronous operation for counting and programming Internal look-ahead for fast counting Carry output for n-bit cascading Fully independent clock circuit Alternate Military Aerospace device (54LS169) is available Contact a National Semiconductor Sales Office Distributor for specifications

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Input Voltage 7V Note The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings The ``Recommended Operating Conditions'' table will define the conditions for actual device operation

Operating Free Air Temperature Range C DM54LS and 70 C Storage Temperature Range

Symbol VCC VIH VIL IOH IOL fCLK tW tSU Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 1) Clock Frequency (Note 2) Clock Pulse Width (Note 3) Setup Time (Note 3) Data Enable or P Load tH TA Hold Time (Note 3) Free Air Operating Temperature

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)

Symbol VI VOH VOL Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Conditions VCC e Min b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIL e Max VIH e Min IOL 4 mA VCC e Min II IIH IIL IOS ICC Input Current Input Voltage Max VCC e Max e 7V VCC e Max 2 7V VCC e Max 0 4V VCC e Max (Note 5) VCC e Max (Note 6) Min Typ (Note

DM54 DM74 Enable T Others Enable T Others Enable T Others DM54 DM74
High Level Input Current Low Level Input Current Short Circuit Output Current Supply Current

Note 4 All typicals are at VCC e 5V and 25 C Note 5 Not more than one output should be shorted at a time and the duration should not exceed one second Note 6 ICC is measured after a momentary 4 5V then ground is applied to the CLOCK with all other inputs grounded and all the outputs open

Switching Characteristics at VCC e 5V and 25 C (See Section 1 for Test Waveforms and Output Load)

2 kX Symbol Parameter From (Input) To (Output) fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Clock to Ripple Carry Clock to Ripple Carry Clock to Any Q Clock to Any Q Enable T to Ripple Carry Enable T to Ripple Carry Up Down to Ripple Carry (Note 1) Up Down to Ripple Carry (Note 15 pF Min Max 50 pF Min Max MHz ns Units

Note 1 The propagation delay from UP DOWN to RIPPLE CARRY must be measured with the counter at either a minimum or a maximum count As the logic level of the up down input is changed the ripple carry output will follow If the count is minimum the ripple carry output transition will be in phase If the count is maximum the ripple carry output will be out of phase



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