56F8357 Datasheet

Hybrid Controller


Features, Applications

to 60 MIPS at 60MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Temperature Sensor Two Quadrature Decoders Optional on-chip regulator FlexCAN module Two Serial Communication Interfaces (SCIs) Up to two Serial Peripheral Interfaces (SPIs) Up to four general-purpose Quad Timers Computer Operating Properly (COP) / Watchdog JTAG/Enhanced On-Chip Emulation (OnCETM) for unobtrusive, real-time debugging to 76 GPIO lines 160-pin LQFP Package

Access 4MB of off-chip program and 32MB of data memory Chip Select Logic for glueless interface to ROM and SRAM 256KB of Program Flash 4KB of Program RAM 8KB of Data Flash 16KB of Data RAM 16KB Boot Flash Two 6-channel PWM modules Four 4-channel, 12-bit ADCs

Current Sense Inputs or GPIOC Fault Inputs PWM Outputs

Current Sense Inputs or GPIOD Fault Inputs AD0 AD1 VREF AD0 AD1 TEMP_SENSE Quadrature Decoder 0 or Quad Timer or / GPIOC Quadrature Decoder 1 or Quad Timer SPI1 or GPIOC Quad Timer C or GPIOE Quad Timer D or GPIOE FlexCAN SPI0 or GPIOE

Data ALU 36 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators

Version History Rev 1.0 Rev 2.0 Description of Change Initial Public Release Added Package Pins to GPIO Table in Part 8, General Purpose Input/Output (GPIO) Added "Typical Min" values to Table 10-17 Editing grammar, spelling, consistency of language throughout family Updated values in Regulator Parameters Table 10-9, External Clock Operation Timing Requirements Table 10-13, SPI Timing Table 10-18, ADC Parameters Table 10-24, and IO Loading Coefficients at 10MHz Table 10-25. Rev 3.0 Rev 4.0 Corrected Table 4-6 Data Memory Map - changed address to X:$FFFF00 Added Section 4.8, added the word "access" to FM Error Interrupt in Table 4-5, documenting only Typ. numbers for LVI in Table 10-6, updated EMI numbers and writeup in Section 10.9. Updated numbers in Table 10-7 and Table 10-8 with more recent data, Corrected typo in Table in Pd characteristics. Replace any reference to Flash Interface Unit with Flash Module; removed references to JTAG pin DE; corrected pin number for D14 in Table 2-2; added note to Vcap pin in Table 2-2; corrected thermal numbers for 160 LQFP in Table 10-3; removed unneccessary notes in Table 10-12; corrected temperature range in Table 10-14; added ADC calibration information to Table 10-24 and new graphs in Figure 10-22 Adding/clarifing notes to Table 4-4 to help clarify independent program flash blocks and other Program Flash modes, clarification in Table 10-23, corrected Digital Input Current Low (pull-up enabled) numbers in Table 10-5. Removed text and Table 10-2; replaced with note to Table 10-1.

1.1. 56F8357 Features. 1.2. 56F8357 Description. 5 1.3. Award-Winning Development Environment. 6 1.4. Architecture Block Diagram. 7 1.5. Product Documentation. 10 1.6. Data Sheet Conventions. 11

Part 9: Joint Test Action Group (JTAG) 122

10.1. General Characteristics. 10.2. DC Electrical Characteristics. 126 10.3. Temperature Sense. 10.4. AC Electrical Characteristics. 129 10.5. Flash Memory Characteristics. 130 10.6. External Clock Operation Timing. 131 10.7. Phase Locked Loop Timing. 131 10.8. Crystal Oscillator Timing. 132 10.9. External Memory Interface Timing. 132 10.10. Reset, Stop, Wait, Mode Select, and Interrupt Timing. 135 10.11. Serial Peripheral Interface (SPI) Timing. 137 10.12. Quad Timer Timing. 141 10.13. Quadrature Decoder Timing. 141 10.14. Serial Communication Interface (SCI) Timing. 142 10.15. Controller Area Network (CAN) Timing. 143 10.16. JTAG Timing. 143 10.17. Analog-to-Digital Converter (ADC) Parameters. 145 10.18. Equivalent Circuit for ADC Inputs. 147 10.19. Power Consumption. 147

Introduction. Program Map. Interrupt Vector Table. Data Map. Flash Memory Map. EOnCE Memory Map. Peripheral Memory Mapped Registers. Factory Programmed Memory.

Overview. 97 Features. 97 Operating Modes. 98 Operation Mode Register. 98 Register Descriptions. 99 Clock Generation Overview. 111 Power Down Modes Overview. 112 Stop and Wait Mode Disable Function 112 Resets. 113

12.1. Thermal Design Considerations. 153 12.2. Electrical Design Considerations. 154 12.3. Power Distribution and I/O Ring Implementation 155

7.1. Operation with Security Enabled. 114 7.2. Flash Access Blocking Mechanisms. 114
Please see http://www.motorola.com/semiconductors for the most current Data Sheet revision.



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