Product Specification Development system runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization Highest capacity--over 180,000 usable gates Additional routing over XQ4000E - Almost twice the routing capacity for high-density designs Buffered Interconnect for maximum speed New latch capability in configurable logic blocks Improved VersaRingTM I/O interconnect for better Fixed pinout flexibility - Virtually unlimited number of clock signals Optional multiplexer or 2-input function generator on device outputs 5V tolerant I/Os 0.35 �m SRAM process
Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing) Ceramic and plastic packages Also available under the following standard microcircuit drawings (SMD) XQ4085XL 5962-99575 For more information contact the Defense Supply Center Columbus (DSCC) http://www.dscc.dla.mis/v/va/smd/smdsrch.html Available in -3 speed System featured Field-Programmable Gate Arrays - SelectRAMTM memory: on-chip ultra-fast RAM with synchronous write option dual-port RAM option - Abundant flip-flops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - Eight global low-skew clock or signal distribution
The QPROTM XQ4000XL Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of thirteen years of FPGA design experience and feedback from thousands of customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated soft-ware to achieve fully automated implementation of complex, high-density, high-performance designs. Refer to the complete Commercial XC4000XL Series Field Programmable Gate Arrays Data Sheet for more information on device architecture and timing, and the latest Xilinx databook for package pinouts other than the CB228 (included in this data sheet). (Pinouts for XQ4000XL device are identical to XC4000XL.)
System performance beyond 50 MHz Flexible array architecture Low power segmented routing architecture Systems-oriented features - IEEE 1149.1-compatible boundary scan logic
- Individually programmable output slew rate - Programmable input pull-up or pull-down resistors 12 mA sink current per XQ4000XL output Configured by loading binary file - Unlimited reprogrammability Readback capability - Program verification - Internal node observability
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Table 1: XQ4000XL Series High Reliability Field Progammable Gate Arrays Max Logic Gates (No RAM)(1) Max. RAM Bits (No Logic) Typical Gate Range (Logic and RAM)(1)Notes: 1. Maximum values of typical gate range includes 30% of CLBs used as RAM.
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Preliminary: Unmarked: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or devicefamilies. Values are subject to change. Use as estimates, not for production. Based on preliminary characterization. Further changes are not expected. Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. All specifications subject to change without notice.
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. For design considerations requiring more detailed timing information, see the appropriate family AC supplements available on the Xilinx web site at: http://www.xilinx.com/partinfo/databook.htm.
Symbol VCC VIN VTS VCCt TSTG TSOL TJ Supply voltage relative to GND Input voltage relative GND(2) output(2) Voltage applied to High-Z Description �65 to Ceramic package Plastic package Units ms �C
Longest supply voltage rise time from to 3V Storage temperature (ambient) Maximum soldering temperature @ 1/16 in. = 1.5 mm) Junction temperature
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. Maximum DC overshoot or undershoot above VCC or below GND must be limited to either or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot V or overshoot to VCC + 2.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
Symbol VCC VIH VIL TIN Description Supply voltage relative to GND, to +125�C Supply voltage relative to GND, to +125�C High-level input voltage(2) Low-level input voltage Input signal transition time Plastic Ceramic Min 50% of VCC 0 Max of VCC 250 Units ns
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per �C. 2. Input and output measurement threshold ~50% of VCC.