Homedatasheet5962F9672401VRC

5962F9672401VRC Datasheet

Radiation Hardened Octal Three-state Transparent Latch
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Description

Features, Applications

Radiation Hardened Octal Three-State Transparent Latch
20 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW
Features

Devices QML Qualified in Accordance with MIL-PRF-38535 Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96724 and Intersil's QM Plan 1.25 Micron Radiation Hardened SOS CMOS Total Dose. >300K RAD (Si) Single Event Upset (SEU) Immunity: x 10-10 Errors/Bit/Day (Typ) SEU LET Threshold. >100 MEV-cm2/mg Dose Rate Upset. >10 Dose Rate Survivability. >10 Latch-Up Free Under Any Conditions Military Temperature Range. +125 C Significant Power Reduction Compared to ALSTTL Logic DC Operating Voltage Range. to 5.5V Input Logic Levels - VIL 30% of VCC Max - VIH 70% of VCC Min Input Current 1�A at VOL, VOH Fast Propagation Delay. 17ns (Max), 12ns (Typ)

20 LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C TOP VIEW
Description

The Intersil is a Radiation Hardened Octal Transparent Latch with an active low output enable. The outputs are transparent to the inputs when the latch enable (LE) is High. When the latch goes low the data is latched. The output enable controls the three-state outputs. When the output enable pins (OE) are high the output in a high impedance state. The latch operation is independent of the state of output enable. The ACS573MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic family. The ACS573MS is supplied a 20 lead Ceramic Flatpack (K suffix) or a

PART NUMBER ACS573K/Sample ACS573HMSR TEMPERATURE RANGE +125oC 25oC SCREENING LEVEL MIL-PRF-38535 Class V MIL-PRF-38535 Class V Sample Die PACKAGE 20 Lead SBDIP 20 Lead Ceramic Flatpack 20 Lead SBDIP 20 Lead Ceramic Flatpack Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Copyright � Intersil Corporation 1999

NOTE: L = Low Logic Level, H = High Logic Level, X = Don't Care, Z = High Impedance, l = Low Voltage Level Prior to High-to-Low Latch Enable Transition, h = High Voltage Level Prior to High-to-Low Latch Enable Transition.

DIE DIMENSIONS: 102 mils x 102 mils x 2,600mm METALLIZATION: Type: AlSi Metal 1 Thickness: 7.125k� �1.125k� Metal 2 Thickness: 9k� �1k� GLASSIVATION: Type: SiO2 Thickness: 8k� �1k� WORST CASE CURRENT DENSITY: 105 A/cm2 BOND PAD SIZE: > 4.3 mils x 4.3 mils x 110�m


Features

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