The is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. Buffered positive edge-triggered clock Asynchronous common reset True and complement output Outputs source/sink mA 'ACT175 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) 'ACT175: 5962-89693Features
Description Data Inputs Clock Pulse Input Master Reset Input True Outputs Complement Outputs
FACT is a registered trademark of Fairchild Semiconductor Corporation.
The 'AC/'ACT175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The 'AC/'ACT175 is useful for general logic applications where a common Master Reset and Clock are acceptable.
H = HIGH Voltage Level L = LOW Voltage Level tn = Bit Time before Clock Pulse tn+1 = Bit Time after Clock Pulse
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = VCC 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = VCC 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP -0.5V to VCC -0.5V to VCC + 0.5V
Supply Voltage (VCC) 'AC 'ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (V/t) 'AC Devices VIN from 70% of VCC 4.5V, 5.5V Minimum Input Edge Rate (V/t) 'ACT Devices VIN from to 2.0V VCC 0V to VCC 0V to VCC to +125�C
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT � circuits outside databook specifications.
Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VCC (V) to +125�C Guaranteed Limits (Note 2) VIN = VIL or VIH IOH mA V IOH -24 mA IOH -24 mA IOUT �A V IOUT �A V VOUT 0.1V or VCC 0.1V V VOUT 0.1V or VCC - 0.1V Units Conditions4.5 5.5 IIN Maximum Input Leakage Current (Note 3) IOLD IOHD Minimum Dynamic Output Current 5.5