Home datasheet 5T2010

5T2010

Clock management
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Features, Applications

2.5 VDD 5 pairs of outputs Low skew: 50ps same pair, 100ps all outputs Selectable positive or negative edge synchronization Tolerant of spread spectrum input clock Synchronous output enable Selectable inputs Input frequency: to 250MHz Output frequency: / 2.5V LVTTL: to 250MHz HSTL / eHSTL: to 250MHz Hot insertable and over-voltage tolerant inputs 3-level inputs for selectable interface 3-level inputs for feedback divide selection with multiply ratios 10, 12) Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input interface Selectable differential or single-ended inputs and ten singleended outputs PLL bypass for DC testing External differential feedback, internal loop filter Low Jitter: <75ps cycle-to-cycle Power-down mode Lock indicator Available in BGA and MLF packages

The a 2.5V PLL clock driver intended for high performance computing and data-communications applications. The IDT5T2010 has ten outputs in five banks of two, plus a dedicated differential feedback. The redundant input capability allows for a smooth change over to a secondary clock source when the primary clock source is absent. The feedback bank allows divide-by-functionality from to 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication to 12 without using divided outputs for feedback. Each output bank also allows for a divide-by functionality or 4. The IDT5T2010 features a user-selectable, single-ended or differential input to ten single-ended outputs. The clock driver also acts as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The outputs can be synchronously enabled/disabled. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.








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