|IDT5T2110 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCKTM
2.5 VDD 6 differential outputs Low skew: 100ps all outputs Selectable positive or negative edge synchronization Tolerant of spread spectrum input clock Synchronous output enable Selectable inputs Input frequency: to 250MHz Output frequency: / 2.5V LVTTL: to 250MHz HSTL / eHSTL: to 250MHz Hot insertable and over-voltage tolerant inputs 3-level inputs for selectable interface 3-level inputs for feedback divide selection with multiply ratios 10, 12) Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input interface Selectable differential or single-ended inputs and six differential outputs PLL bypass for DC testing External differential feedback, internal loop filter Low Jitter: <75ps cycle-to-cycle Power-down mode Lock indicator Available in BGA and MLF package
The a 2.5V PLL differential clock driver intended for high performance computing and data-communications applications. The IDT5T2110 has six differential outputs in six banks, including a dedicated differential feedback. The redundant input capability allows for a smooth change over to a secondary clock source when the primary clock source is absent. The feedback bank allows divide-by-functionality from to 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication to 12 without using divided outputs for feedback. Each output bank also allows for a divide-by functionality or 4. The 5T2110 features a user-selectable, single-ended or differential input to six differential outputs. The differential clock driver also acts as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The differential outputs can be synchronously enabled/disabled. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF.
PE FS LOCK PLL_EN FB FB/ /N 3 PLL 0 1 RxS REF1/ VREF1 REF_SEL 4F2:1 Divide Select Divide Select 2F2:1 Divide Select Divide SelectThe IDT logo is a registered trademark of Integrated Device Technology, Inc.