Home datasheet 5T9050

5T9050

Clock management
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IDT5T9050 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFERTM JR.

Optimized for 2.5V LVTTL Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 300 (max) High speed propagation delay < 1.8ns. (max) to 200MHz operation Very low CMOS power levels Hot insertable and over-voltage tolerant inputs 1:5 fanout buffer 2.5V VDD Available in TSSOP package

The IDT5T9050 2.5V single data rate (SDR) clock buffer is a single-ended input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. Multiple power and grounds reduce noise.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Symbol VDD Description Power Supply Voltage Input Voltage Output Voltage Storage Temperature Junction Temperature Max �0.5 to VDD +165 150 Unit VI VO TSTG TJ

NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Symbol CIN Parameter Input Capacitance Min Typ. 6 Max. Unit pF
NOTE: 1. This parameter is measured at characterization but not tested.

Symbol TA VDD Description Ambient Operating Temperature Internal Power Supply Voltage Min. �40 2.3 Typ. +25 2.5 Max. +85 2.7 Unit �C V

Symbol GL Qn VDD GND I/O Type LVTTL PWR Description Clock input Gate control for Qn outputs. When G is LOW, these outputs are enabled. When G is HIGH, these outputs are asynchronously disabled to the level designated by GL(1). Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW. Clock outputs Power supply for the device core, inputs, and outputs Power supply return for power

NOTE: 1. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.

Symbol IIH IIL VIK VIN VIH VIL VOH VOL Parameter Input HIGH Current Input LOW Current Clamp Diode Voltage DC Input Voltage DC Input HIGH(2) DC Input LOW(3) Output HIGH Voltage Output LOW Voltage Test Conditions VDD VI = VDD/GND VDD VI = GND/VDD VDD = 2.3V, IIN = -18mA Min. 0.3 1.7 VDD - 0.4 VDD - 0.7 Max Unit �A

NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. Voltage required to maintain a logic HIGH. 3. Voltage required to maintain a logic LOW. 4. Typical values are at VDD 2.5V, +25�C ambient.

Symbol IDDQ IDDD ITOT Parameter Quiescent VDD Power Supply Current Dynamic VDD Power Supply Current per Output Total Power VDD Supply Current Test Conditions(1) VDD = Max., Reference Clock = LOW Outputs enabled, All outputs unloaded VDD = Max., = 0pF VDD = 2.5V., FREFERENCE CLOCK = 15pF VDD = 2.5V., FREFERENCE CLOCK = 15pF Typ. Max Unit mA � A/MHz mA

NOTE: 1. The termination resistors are excluded from these measurements.

Symbol VIH VIL VTH tR, tF Parameter Input HIGH Voltage Input LOW Voltage Input Timing Measurement Reference Level(1) Input Signal Edge Rate(2) Value VDD VDD/2 2 Units V V/ns

NOTES: 1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 2. The input signal edge rate 2V/ns or greater to be maintained in the to 90% range of the input waveform.


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