5T9950 Datasheet

2.5V Programmable Skew PLL Clock Driver Turboclock ii Jr.


Features, Applications

Ref input is 3.3V tolerant 4 pairs of programmable skew outputs Low skew: 185ps same pair, 250ps all outputs Selectable positive or negative edge synchronization: Excellent for DSP applications Synchronous output enable Input frequency: � Std: to 200MHz Output frequency: � Std: 4x, 1/2, and 1/4 outputs 3-level inputs for skew and PLL range control PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: <100ps cycle-to-cycle Standard and A speed grades Available in TQFP package

The is a high fanout 2.5V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5T9950 has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are synchronously disabled. The LOCK output asserts to indicate when Phase Lock has been achieved. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The IDT5T9950 has LVTTL outputs with 12mA balanced drive outputs.

Skew Select 1F1:0 PE TEST Skew Select 3 PLL FB 3 Skew Select 3 2F1:0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Symbol VDDQ, VDD VI Description Supply Voltage to Ground DC Input Voltage REF Input Voltage Maximum Power

NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.

Parameter Description Input Capacitance Typ. 5 Max. 7 Unit pF CIN

Pin Name REF FB TEST (1) sOE(1) Type IN Description Reference Clock Input Feedback Input When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary Table) remain in effect. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and in a LOW state (for - 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull-down). Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock (has internal pull-up). FS nQ[1:0] VDDQ VDD GND IN OUT PWR 3-level inputs for selecting of 9 skew taps or frequency functions Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.) Four banks of two outputs with programmable skew Power supply for output buffers Power supply for phase locked loop, lock output, and other internal circuitry Ground

NOTE: 1. When TEST = MID and sOE = HIGH, PLL remains active with = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL.

NOTE: 1. Capacitance applies to all inputs except TEST, FS, nF[1:0], and DS[1:0].

Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit (tU) which ranges from to 1.5625ns for Standard version and to 1.3ns for A version (see Programmable Skew Range and Resolution Table). There are nine skew configurations available for each output pair. These configurations are chosen by the nF1:0 control pins. In order to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Control Summary Table shows how to select specific skew taps by using the nF1:0 control pins.

By providing external feedback, the IDT5T9950 gives users flexibility with regard to skew adjustment. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.

FS = LOW Timing Unit Calculation (tU) VCO Frequency Range (FNOM)(1,2) Skew Adjustment Range(3) Max Adjustment: �67.5� �18.75% Example 1, FNOM = 25MHz Example 2, FNOM = 37.5MHz Example 3, FNOM = 50MHz Example 4, FNOM = 75MHz Example 5, FNOM = 100MHz Example 6, FNOM = 150MHz Example 7, FNOM 0.625ns ns Phase Degrees % of Cycle Time 1/(32 x FNOM) FS = MID 1/(16 x FNOM) FS = HIGH 1/(8 x FNOM) FS = LOW FS = MID FS = HIGH 1/(8 x FNOM) to 200MHz Comments 1/(32 x FNOM) 1/(16 x FNOM) to 100MHz

NOTES: 1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. 2. The level to be set FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected FB is undivided. The frequency of the REF and FB inputs will or 1/4 the VCO frequency when the part is configured for frequency multiplication by using a divided output as the FB input. 3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example a 4tU skewed output is used for feedback, all other outputs will be skewed �4tU in addition to whatever skew value is programmed for those outputs. `Max adjustment' range applies to output pairs 3 and 4 where � 6tU skew adjustment is possible and at the lowest FNOM value.



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