Homedatasheet7005

7005 Datasheet

Multi-Ports
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Description

Features, Applications
Features

True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access Military: 20/25/35/55/70ns (max.) Industrial: 35/55ns (max.) Commercial:15/17/20/25/35/55ns (max.) Low-power operation IDT7005S Active: 750mW (typ.) Standby: 5mW (typ.) IDT7005L Active: 700mW (typ.) Standby: 1mW (typ.) IDT7005 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than

one device M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Devices are capable of withstanding greater than 2001V electrostatic discharge Battery backup operation2V data retention TTL-compatible, single 5V (�10%) power supply Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin thin quad flatpack Industrial temperature range +85�C) is available for selected speeds

NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull.

The is a high-speed x 8 Dual-Port Static RAM. The IDT7005 is designed to be used as a stand-alone 64K-bit Dual-Port RAM as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach 16-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter

Description

a very low standby power mode. Fabricated using IDTs CMOS high-performance technology, these devices typically operate on only 750mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500�W from a 2V battery. The IDT7005 is packaged in a ceramic 68-pin PGA, 68-pin quad flatpack, 68-pin PLCC and a 64-pin thin quad flatpack, (TQFP). Military grade product is manufactured in compliance with the latest revision of MILPRF-38535 QML making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. J68-1 package body in x.12 in. F68-1 package body in x.08 in. PN64 package body is approximately 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate oriention of the actual part-marking


NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately x.16in. 4. This package code is used to reference the package diagram. 5. This text does not indicate oriention of the actual part-marking

Left Port CEL R/ WL OEL - I/O7L SEML INTL BUSYL CER R/ WR OER - I/O7R SEMR INTR BUSYR M/S VCC GND Right Port Names Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master or Slave Select Power Ground


Features

Parameters

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