74AHC132D,112 Datasheet

Logic Gates


The 74AHC132D,112 ; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specied in compliance with JEDEC standard No. 7-A. The 74AHC132D,112; 74AHCT132 contains four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply dened, jitter free output signals. The gate switches at different points for positive-going and negative-going signals. The difference between the positive voltage VT+ and the negative VT− is dened as the hysteresis voltage VH. 74AHC132D,112 Features • Balanced propagation delays• Inputs accept voltages higher than VCC• Input levels:- For 74AHC132: CMOS level- For 74AHCT132: TTL level• ESD protection:- HBM EIA/JESD22-A114E exceeds 2000 V- MM EIA/JESD22-A115-A exceeds 200 V- CDM EIA/JESD22-C101C exceeds 1000 V• Multiple package options


[{"Name":"Number of Gates:","Value":"4"},{"Name":"Number of Lines (Input / Output):","Value":"2 / 1"},{"Name":"High Level Output Current:","Value":"-8 mA"},{"Name":" Low Level Output Current:","Value":"8 mA"},{"Name":" Propagation Delay Time:","Value":"3.3 ns"},{"Name":"Supply Voltage - Max:","Value":"5.5 V"},{"Name":"Supply Voltage - Min:","Value":"2 V"},{"Name":"Maximum Operating Temperature:","Value":"+ 125 C"},{"Name":"Minimum Operating Temperature:","Value":"- 40 C"},{"Name":"","Value":""}]

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