74HCT646DB Datasheet

Logic - Buffers, Drivers, Receivers, Transceivers


The 74HC646, 74HCT646DB are high-speed Si-gate CMOS devicesand are pin compatible with low power Schottky TTL(LSTTL). They are specified in compliance with JEDECstandard no. 7A.The 74HC/HCT646 consist of bus transceiver circuits with3-state outputs, D-type flip-flops, and control circuitryarranged for multiplexed transmission of data directly fromthe internal registers. Data on the “A” or “B” bus will beclocked into the registers as the appropriate clock(CPAB and CPBA) goes to a HIGH logic level. Outputenable (OE) and direction (DIR) inputs are provided tocontrol the transceiver function. In the transceiver mode,data present at the high-impedance port may be stored ineither the “A” or “B” register, or in both. The select sourceinputs (SAB and SBA) can multiplex stored and real-time(transparent mode) data. The direction (DIR) inputdetermines which bus will receive data when OE is active(LOW). In the isolation mode (OE = HIGH), “A” data maybe stored in the “B” register and/or “B” data may be storedin the “A” register.When an output function is disabled, the input function isstill enabled and may be used to store and transmit data.Only one of the two buses, A or B, may be driven at a time.The “646” is functionally identical to the “648”, but hasnon-inverting data paths. 74HCT646DB Features • Independent register for A and B buses• Multiplexed real-time and stored data• Output capability: bus driver• ICC category: MSI


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