74LVC1G19GW Datasheet

Logic - Signal Switches, Multiplexers, Decoders


The 74LVC1G19GW is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC1G19GW is a 1-of-2 decoder/demultiplexer with a common output enable. The 74LVC1G19GW buffers the data on input pin E and passes it either to output pin 1Y or 2Y, depending on whether the state of the select input pin A is LOW or HIGH, respectively. 74LVC1G19GW Features • Wide supply voltage range from 1.65 V to 5.5 V• 5 V tolerant inputs for interfacing with 5 V logic• High noise immunity• Complies with JEDEC standard:– JESD8-7 (1.65 V to 1.95 V)– JESD8-5 (2.3 V to 2.7 V)– JESD8B/JESD36 (2.7 V to 3.6 V).• ESD protection:– HBM EIA/JESD22-A114-B exceeds 2000 V– MM EIA/JESD22-A115-A exceeds 200 V.• ±24 mA output drive (VCC = 3.0 V)• CMOS low power consumption• Latch-up performance exceeds 250 mA• Direct interface with TTL levels• Multiple package options


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