1 8 VDD All-silicon, low-power CMOS 7 O1 technology 6 O3 GND 5 O5 TTL/CMOS compatible inputs and outputs 3D7105Z Vapor phase, IR and wave SOIC (150 Mil) solderable Auto-insertable (DIP pkg.) Low ground bounce noise Leading- and trailing-edge accuracy Delay range:.75 through 80ns Delay tolerance: or 1ns Temperature stability: �3% typical (0C-70C) Vdd stability: �1% typical (4.75V-5.25V) Minimum input pulse width: 30% of total delay 14-pin DIP and 16-pin SOIC available as drop-in replacements for hybrid delay lines
The 3D7105 5-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 0.75ns through 8.0ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7105 is TTL- and CMOScompatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.
O4 O5 VCC GND N/C Delay Line Input Tap 1 Output (20%) Tap 2 Output (40%) Tap 3 Output (60%) Tap 4 Output (80%) Tap 5 Output (100%) +5 Volts Ground No Connection
The all-CMOS 3D7105 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.TOTAL DELAY (ns) TAP-TAP DELAY (ns) Max Operating Frequency
Absolute Max Oper. Freq. Min Operating Pulse Width Absolute Min Oper. P.W.
The 3D7105 five-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-to-tap delay deviations over temperature and supply voltage variations. To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D7105 must be tested at the user operating frequency. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.
The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified.
The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed. To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D7105 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a
The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.
custom reference designator identifying the intended frequency and duty cycle of operation. The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted. circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. The thermal coefficient is reduced to 600 PPM/C, which is equivalent to a variation , over the 0C-70C operating range, of �3% from the room-temperature delay settings and/or 1.0ns, whichever is greater. The power supply coefficient is reduced, over the 4.75V-5.25V operating range, �1% of the delay settings at the nominal 5.0VDC power supply and/or 1.5ns, whichever is greater. It is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should of as low an impedance construction as possible. Power planes are preferred.
The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The monolithic 3D7105 programmable delay line utilizes novel and innovative compensation
PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN MAX 150 300 UNITS mA C NOTES
to 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH IOL & TF MIN MAX 40 UNITS mA ns NOTES
*IDD(Dynamic) 5 * CLD * VDD * F where: CLD = Average capacitance load/tap (pf) F = Input frequency (GHz)Input Capacitance 10 pf typical Output Load Capacitance (CLD) 25 pf max