All-silicon, low-power 3.3V CMOS technology Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Low ground bounce noise Leading- and trailing-edge accuracy Delay range: 1.5ns through 300ns Total delay tolerance: (3.3V, 25C) Temperature stability: �1% typical (0C-70C) Vdd stability: �1% typical (3.0V-3.6V) Static Idd: 1.3ma typical Minimum input pulse width: 25% of total delay
3D3215M-xx DIP (300 Mil) For mechanical dimensions, click here. For package marking details, click here.
The 3D3215 5-Tap Delay Line product family consists of fixed-delay 3.3V CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 5 points spaced uniformly in time. Tap-totap (incremental) delay values can range from 1.5ns through 60ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The is 3.3V CMOScompatible and features both rising- and falling-edge accuracy.
O4 O5 VDD GND N/C Delay Line Input Tap 1 Output (20%) Tap 2 Output (40%) Tap 3 Output (60%) Tap 4 Output (80%) Tap 5 Output (100%) +3.3 Volts Ground No Connection
The all-CMOS 3D3215 integrated circuit has been designed as a reliable, economic alternative to hybrid fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.
* Total delay referenced to Tap1 output; � 1.5ns NOTE: Any dash number between 1.5 and 60 not shown is also available as standard � 2001 Data Delay Devices
The 3D3215 five-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-to-tap delay deviations over temperature and supply voltage variations. delay accuracy is guaranteed. To guarantee the Table 1 delay accuracy for input frequencies higher than the Recommended Maximum Frequency, the 3D3215 must be tested at the user operating frequency. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.
The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Recommended Maximum and an Absolute Maximum operating input frequency and a Recommended Minimum and an Absolute Minimum operating pulse width have been specified.
The Absolute Minimum Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. The Recommended Minimum Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed. To guarantee the Table 1 delay accuracy for input pulse width smaller than the Recommended Minimum Pulse Width, the 3D3215 must be tested at the user operating pulse width. Therefore, to facilitate production and device
The Absolute Maximum Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. The Recommended Maximum Frequency specification determines the highest frequency of the delay line input signal for which the output O4 O5
identification, the part number will include a custom reference designator identifying the intended frequency and duty cycle of operation. The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted. The thermal coefficient is reduced to 200 PPM/C, which is equivalent to a variation, over the 0C70C operating range, or 0.25ns (whichever is greater) from the 25C delay settings. The power supply coefficient is reduced, over the 3.0V-3.6V operating range, or 1ns (whichever is greater) of the delay settings at the nominal 3.3VDC power supply. The temperature and power supply sensitivities are based on the measured delay of Tap 5 with respect to Tap 1. The sensitivity of the Input-toTap 1 delay will be somewhat higher, particularly with the smaller dash numbers. It is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should of as low an impedance construction as possible. Power planes are preferred.
The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The monolithic 3D3215 delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature.
PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN MAX 150 300 UNITS mA C NOTES
to 3.6V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH IOL & TF MIN TYP 1.3 MAX 2.0 UNITS mA ns NOTES VDD = 3.6V
*IDD(Dynamic) 5 * CLD * VDD * F where: CLD = Average capacitance load/tap (pf) F = Input frequency (GHz)Input Capacitance 10 pf typical Output Load Capacitance (CLD) 25 pf max