MONOLITHIC QUAD FIXED DELAY LINE (SERIES 3D3314)
All-silicon, low-power 3.3V CMOS technology Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Low ground bounce noise Leading- and trailing-edge accuracy Delay range: 10ns through 400ns Delay tolerance: (3.3V, 25C) Temperature stability: �1% typical (0C-70C) Vdd stability: �1% typical (3.0V-3.6V) Static Idd: 1.3ma typical Minimum input pulse width: 25% of total delay(For mechanical data, see Case Dimensions document)
The 3D3314 device is a small, versatile, quad fixed monolithic delay line. Delay values ranging from 10ns through 400ns may be specified via the device dash number. Each input is reproduced at the corresponding output without inversion, shifted in time as per user selection. The is 3.3V CMOS-compatible and features both rising- and falling-edge accuracy. The device is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 14-pin SOIC.I1-I4 O1-O4 VDD GND NC Signal Inputs Signal Outputs 3.3V Ground No Connection
RECOMMENDED Max Freq Min P.W. 40.0 MHz ns 26.6 MHz ns 20.0 MHz ns 16.0 MHz ns 13.3 MHz ns 10.0 MHz ns 8.00 MHz ns 5.33 MHz ns 4.00 MHz ns 3.20 MHz ns 2.66 MHz ns 2.00 MHz ns 1.60 MHz ns 1.33 MHz ns 1.00 MHz 500.0 ns ABSOLUTE Max Freq Min P.W. 166 MHz ns 166 MHz ns 166 MHz ns 166 MHz ns 166 MHz ns 125 MHz ns 100 MHz ns 66.6 MHz ns 50.0 MHz ns 40.0 MHz ns 33.3 MHz ns 25.0 MHz ns 20.0 MHz ns 16.6 MHz ns 12.5 MHz 40.0 ns
NOTES: Any dash number between 10 and 400 not shown is also available as standard � 2002 Data Delay Devices
The 3D3314 quad fixed delay line architecture is shown in Figure 1. Each delay line is composed of a number of delay cells connected in series. Each delay line produces at its output a replica of the signal present at its input, shifted in time. The delay lines are matched and share the same compensation signals, which minimizes line-toline delay deviations over temperature and supply voltage variations. Table 1 delay accuracy for input frequencies higher than the Recommended Maximum Frequency, the 3D3314 must be tested at the user operating frequency. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.
The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Recommended Maximum and an Absolute Maximum operating input frequency and a Recommended Minimum and an Absolute Minimum operating pulse width have been specified.
The Absolute Minimum Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. The Recommended Minimum Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed. To guarantee the Table 1 delay accuracy for input pulse width smaller than the Recommended Minimum Pulse Width, the 3D3314 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency and duty cycle of operation. O3 O4
The Absolute Maximum Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. The Recommended Maximum Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. To guarantee the VDD O1
The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted. the delay variations induced by fluctuations in power supply and/or temperature. The thermal coefficient is reduced to 200 PPM/C, which is equivalent to a variation, over the 0C70C operating range, or 0.25ns (whichever is greater) from the 25C delay settings. The power supply coefficient is reduced, over the 3.0V-3.6V operating range, or 1ns (whichever is greater) of the delay settings at the nominal 3.3VDC power supply. It is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should of as low an impedance construction as possible. Power planes are preferred.
The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The monolithic 3D3314 delay line utilizes novel and innovative compensation circuitry to minimize
PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN MAX 150 300 UNITS mA C NOTES
to 3.6V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH IOL & TF MIN TYP 1.3 MAX 2.0 UNITS mA ns NOTES VDD = 3.6V
*IDD(Dynamic) 4 * CLD * VDD * F where: CLD = Average capacitance load/line (pf) F = Input frequency (GHz)Input Capacitance 10 pf typical Output Load Capacitance (CLD) 25 pf max