1032-90LJ Datasheet

High-density Programmable Logic


Features, Applications

HIGH-DENSITY PROGRAMMABLE LOGIC High Speed Global Interconnect 6000 PLD Gates 64 I/O Pins, Eight Dedicated Inputs 192 Registers Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Fast Random Logic Security Cell Prevents Unauthorized Copying HIGH PERFORMANCE E2CMOS� TECHNOLOGY fmax = 90 MHz Maximum Operating Frequency fmax = 60 MHz for Industrial and Military/883 Devices tpd 12 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable Non-Volatile E2CMOS Technology 100% Tested ispLSI OFFERS THE FOLLOWING ADDED FEATURES In-System ProgrammableTM (ISPTM) 5-Volt Only Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and Structured Designs Four Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity ispLSI AND pLSI DEVELOPMENT TOOLS pDS� Software Easy to Use PC WindowsTM Interface Boolean Logic Compiler Manual Partitioning Automatic Place and Route Static Timing Table ispDS+TM Software Industry Standard, Third Party Design Environments Schematic Capture, State Machine, HDL Automatic Partitioning and Place and Route Comprehensive Logic and Timing Simulation PC and Workstation Platforms


The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032 features 5-Volt insystem programming and in-system diagnostic capabilities. It is the first device which offers non-volatile "on-the-fly" reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1032 device, but multiplexes four of the dedicated input pins to control in-system programming. The basic unit of logic on the ispLSI and pLSI 1032 devices is the Generic Logic Block (GLB). The GLBs are labeled A1.. D7 (see figure 1). There are a total of 32 GLBs in the ispLSI and pLSI 1032 devices. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com

Figure 1. ispLSI and pLSI 1032 Functional Block Diagram
Input Bus Generic Logic Blocks (GLBs) D7 D6 Output Routing Pool (ORP) D1 D0

The devices also have 64 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output drivers can source mA or sink 8 mA. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. The I/O cells within the Megablock also share a common Output Enable (OE) signal. The ispLSI and pLSI 1032 devices contain four of these Megablocks.

The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI and pLSI 1032 devices are selected using the Clock Distribution Network. Four dedicated clock pins Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (C0 on the ispLSI and pLSI 1032 devices). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.

Supply Voltage to +7.0V Input Voltage Applied........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied..... -2.5 to VCC +1.0V Storage Temperature................................ to 150�C Case Temp. with Power Applied.............. to 125�C Max. Junction Temp. (TJ) with Power Applied... 150�C

1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications).

SYMBOL PARAMETER Dedicated Input Capacitance I/O and Clock Capacitance Commercial/Industrial Military 8 10 UNITS pf TEST CONDITIONS V CC=5.0V, VI/O, VY=2.0V

PARAMETER Data Retention ispLSI Erase/Reprogram Cycles pLSI Erase/Reprogram Cycles MINIMUM 10000 100 MAXIMUM � UNITS Years Cycles



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