Single supply with operation down to 1.8V Low power CMOS technology 1 mA active current typical 10 �A standby current typical 3 �A standby current typical at 1.8V Organized or 4 blocks of 256 bytes 8) 2-wire serial interface bus, I2CTM compatible Schmitt trigger, filtered inputs for noise suppression Output slope control to eliminate ground bounce 100 kHz (1.8V) and 400 kHz (5V) compatibility Self-timed write cycle (including auto-erase) Page-write buffer for to 16 bytes 2 ms typical write cycle time for page-write Hardware write protect for entire memory Can be operated as a serial ROM ESD protection 4,000V 1,000,000 ERASE/WRITE cycles guaranteed Data retention > 200 years 8-pin DIP, or 14-lead SOIC packages Available for extended temperature ranges - Commercial (C): +70�C - Industrial (I): to +85�CDESCRIPTION
The Microchip Technology Inc. a 4K bit or 8K bit Electrically Erasable PROM. The device is organized as two or four blocks x 8-bit memory with a two wire serial interface. Low voltage design permits operation down to 1.8 volts with standby and active currents of only 3 �A and 1 mA respectively. The 24AA04/ 08 also has a page-write capability for to 16 bytes of data. The 24AA04/08 is available in the standard 8-pin DIP and both 8-lead and 14-lead surface mount SOIC packages.
Function Ground Serial Address/Data I/O Serial Clock Write Protect Input to 5.5V Power Supply No Internal Connection
VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS.............. -0.6V to VCC +1.0V Storage temperature..................................... to +150�C Ambient temp. with power applied................ to +125�C Soldering temperature of leads (10 seconds)............. +300�C ESD protection on all pins.................................................. 4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
VCC to +5.5V Commercial (C): Tamb to +70�C Industrial (I): Tamb to +85�C Parameter Sym VIH VIL VHYS VOL ILI ILO CIN, COUT ICC WRITE Min.7 Vcc --.05 VCC -10 Typ Max --.3 VCC Units mA �A Conditions
0.5 ICC READ 0.05 Standby current ICCS 3 Note:This parameter is periodically sampled and not 100% tested.
WP, SCL and SDA pins: High level input voltage Low Level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current
(Note) IOL = 3.0 mA, VCC = 1.8V VIN =.1V to VCC VOUT =.1V to VCC = 5.0V (Note 1) Tamb = 25�C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 1.8V, SCL = 100 kHz VCC = 5.5V, SCL = 400 kHz VCC = 1.8V, SCL = 100 kHz VCC = 5.5V, SDA=SCL=VCC VCC = 3.0V, SDA=SCL=VCC VCC = 1.8V, SDA=SCL=VCC
Standard Mode Parameter Symbol Min Clock frequency Fclk Clock high time Thigh Clock low time Tlow SDA and SCL rise time Tr SDA and SCL fall time Tf START condition hold time THD:STA START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time Output fall time from VIH min to VIL max Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance 24AA04 24AA08 TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF TOF TSP TWR 10M 1M Max VCC = 4.5-5.5V Fast Mode Min 10M 1M Max kHz ns
(Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition(Note 2) Time the bus must be free before a new transmission can start (Note 100 pF (Note 3)
ms Byte or Page mode cycles 25�C, Vcc = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.TSU:STA THD:STA THD:DAT TSP TAA TBUF TSU:DAT TSU:STO