Homedatasheet24C01A-P

24C01A-P Datasheet

1k/2k/4k 5.0v i 2 C o Serial EePROMs
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Description

Features, Applications
FEATURES

Low power CMOS technology Hardware write protect Two wire serial interface bus, I2CTM compatible 5.0V only operation Self-timed write cycle (including auto-erase) Page-write buffer 1ms write cycle time for single byte 1,000,000 Erase/Write cycles guaranteed Data retention >200 years 8-pin DIP/SOIC packages Available for extended temperature ranges - Commercial (C): +70�C - Industrial (I): +85�C - Automotive (E): to +125�C

DESCRIPTION

The Microchip Technology Inc. a 1K/2K/4K bit Electrically Erasable PROM. The device is organized as shown, with a standard two wire serial interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. A special feature in the 24C02A and 24C04A provides hardware write protection for the upper half of the block. The 24C01A and 24C02A have a page write capability of two bytes and the 24C04A has a page length of eight bytes. Up to eight or 24C02A devices and up to four 24C04A devices may be connected to the same two wire bus. This device offers fast (1ms) byte write and extended to 125�C) temperature operation. It is recommended that all other applications use Microchip's 24LCXXB. 24C01A Organization Write Protect Page Write Buffer x 8 None 2 Bytes 080-0FF 2 Bytes 100-1FF 8 Bytes 14-lead SOIC

Function No Function for 24C04A only, Must be connected to VCC or VSS Chip Address Inputs Ground Serial Address/Data I/O Serial Clock (24C01A only) VCC or VSS Write Protect Input +5V Power Supply

VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS............... -0.6V to VCC +1.0V Storage temperature..................................... to +150�C Ambient temp. with power applied................ to +125�C Soldering temperature of leads (10 seconds)............. +300�C ESD protection on all pins................................................4 kV

*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Commercial (C): Tamb to +70�C Industrial (I): Tamb to +85�C Automotive (E): Tamb to +125�C Symbol Min. Max. Units pF mA Conditions

VCC detector threshold VTH 2.8 4.5 SCL and SDA pins: High level input voltage VIH VCC x 0.7 VCC + 1 Low level input voltage -0.3 VCC x 0.3 VIL Low level output voltage VOL & A2 pins: High level input voltage VIH VCC - 0.5 VCC + 0.5 Low level input voltage VIL 0.5 10 Input leakage current ILI Output leakage current ILO 10 Pin capacitance CIN, 7.0 (all inputs/outputs) COUT Operating current ICC Write 3.5 ICC Write 4.25

ICC 750 �A Read 100 �A Standby current ICCS Note: This parameter is periodically sampled and not 100% tested

VIN 0V to VCC VOUT 0V to VCC VIN/VOUT = 0V (Note) Tamb = 1 MHz FCLK = 100 kHz, program cycle time = 1 ms, Vcc = 5V, Tamb to +70�C FCLK = 100 kHz, program cycle time = 1 ms, Vcc = 5V, Tamb = (I) and (E) VCC = 5V, Tamb= (C), (I) and (E) SDA=SCL=VCC=5V (no PROGRAM active)

Symbol FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TAA TSU:STO TBUF Min. Typ Max. Units kHz ns (Note 1) ns Time the bus must be free before a new transmission can start Remarks Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time Data output delay time STOP condition setup time Bus free time

After this period the first clock pulse is generated Only relevant for repeated START condition
Input filter time constant (SDA and SCL pins) Program cycle time

Byte mode Page mode, N=# of bytes Endurance 1M 25�C, Vcc = 5.0V, Block Mode (Note 2) Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.


Features

Parameters

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