Homedatasheet24LC128-ESN

24LC128-ESN Datasheet

I2c�� Serial Eeprom Family Data Sheet
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Features, Applications

128-bit through 512 Kbit devices Single supply with operation down to 1.7V for 24AAXX devices Low-power CMOS technology: 1 mA active current, typical 1 A standby current, typical (I-temp) 2-wire serial interface bus, I2CTM compatible Schmitt Trigger inputs for noise suppression Output slope control to eliminate ground bounce 100 kHz (1.7V) and 400 kHz ( 2.5V) compatibility 1 MHz for 24FCXX products Self-timed write cycle (including auto-erase) Page write buffer Hardware write-protect available on most devices Factory programming (QTP) available ESD protection 4,000V 1 million erase/write cycles Data retention > 200 years 8-lead PDIP, SOIC, TSSOP and MSOP packages 5-lead SOT-23 package (most 1-16 Kbit devices) 8-lead 2x3mm and 5x6mm DFN packages available Pb-free and RoHS compliant Available for extended temperature ranges: - Industrial (I): +85�C - Automotive (E): to +125�C

The Microchip Technology Inc. 24LCXX, 24AAXX and 24FCXX (24XX*) devices are a family of 128-bit through 512 Kbit Electrically Erased PROMs. The devices are organized in blocks of x8-bit memory with 2-wire serial interfaces. Low-voltage design permits operation down to 1.7V (for 24AAXX devices), with standby and active currents of only 1 A and 1 mA, respectively. Devices 1 Kbit and larger have page write capability. Parts having functional address lines allow connection to 8 devices on the same bus. The 24XX family is available in the standard 8-pin PDIP, surface mount SOIC, TSSOP and MSOP packages. Most 128-bit through 16 Kbit devices are also available in the 5-lead SOT-23 package. DFN packages or 5x6mm) are also available. All packages are Pb-free (Matte Tin) finish.

*24XX is used in this document as a generic part number for 24 series devices in this data sheet. 24XX64, for example, represents all voltages of the 64 Kbit device.

Pins A1, A2 and WP are not used by some devices (no internal connections). See Table 1-1, Device Selection Table, for details. Pins A0 and A1 are no-connects for the 24XX128 and 24XX256 MSOP devices. Pin 7 is "not used" for 24XX00, 24XX025 and 24C01C.

Part Number 128-bit devices 1 Kb devices 2 Kb devices 4 Kb devices 8 Kb devices 16 Kb devices 32 Kb devices 64 Kb devices 1.7-5.5V 400 kHz (2) 400 kHz MHz(3) 32 bytes Entire Array I P, SN, SM, ST, MS, 2.5-5.5V 400 kHz (2) 400 kHz 32 bytes Entire Array E P, SN, SM, ST, MS, 2.5-5.5V 400 kHz (2) 400 kHz 16 bytes Entire Array None E P, SN, ST, MS, OT, 2.5-5.5V 400 kHz (2) 400 kHz 16 bytes Entire Array None E P, SN, ST, MS, OT, 2.5-5.5V 400 kHz (2) 400 kHz 16 bytes Entire Array None E P, SN, ST, MS, OT, 4.5-5.5V 400 kHz (2) 400 kHz kHz(2) 400 kHz kHz(2) 400 kHz 400 kHz 8 bytes 16 bytes 16 bytes 16 bytes Entire Array Entire Array None Upper Half of Array None E P, SN, ST, MC P, SN, ST,MS, MC P, SN, ST, MS, MC P, SN, ST, MS, OT, 2.5-5.5V 400 kHz (2) 400 kHz 400 kHz 400 kHz

VCC Range Max. Clock Frequency Page Size WriteProtect Scheme Functional Address Pins Temp. Range Packages(5)

Note 1: 100 kHz for VCC 2: 100 kHz for VCC 3: 400 kHz for VCC <2.5V. 4: Pins A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package. (3.90 mm JEDEC), = 2x3mm DFN, 8-SOIC (200 mil EIAJ), = 5x6mm DFN.

Part Number 128 Kb devices 256 Kb devices 512 Kb devices 2.5-5.5V 400 kHz (2) 400 kHz 128 bytes I Entire Array I P, SM, MF, 1.7-5.5V 400 kHz (2) 400 kHz MHz(3) 64 bytes Entire Array I P, SN, SM, ST, MS, MF, 1.7-5.5V 400 kHz (2) 400 kHz MHz(3) 64 bytes Entire Array I P, SN, SM, ST, MS, MF, ST14

Note 1: 100 kHz for VCC 2: 100 kHz for VCC 3: 400 kHz for VCC <2.5V. 4: Pins A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package. (3.90 mm JEDEC), = 2x3mm DFN, 8-SOIC (200 mil EIAJ), = 5x6mm DFN.


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