Voltage operating range: 6.0V - Peak write current 6.0V - Maximum read current 6.0V - Standby current 1 �A typical Industry standard two-wire bus protocol, I2C compatible - Including 100 kHz (2.5V) and 400 kHz (5V) modes Self-timed ERASE and WRITE cycles Power on/off data protection circuitry Endurance: - 10,000,000 Erase/Write cycles guaranteed for High Endurance Block - 1,000,000 E/W cycles guaranteed for Standard Endurance Block 8 byte page, or byte modes available 1 page x 8 line input cache (64 bytes) for fast write loads Schmitt trigger, filtered inputs for noise suppression Output slope control to eliminate ground bounce 2 ms typical write cycle time, byte or page Factory programming (QTP) available to 8 devices may be connected to the same bus for to 256K bits total memory Electrostatic discharge protection > 4000V Data retention > 200 years 8-pin PDIP/SOIC packages Temperature ranges - Commercial (C): +70�C - Industrial (I): to +85�DESCRIPTION
The Microchip Technology Inc. 8 (32K bit) Serial Electrically Erasable PROM capable of operation across a broad voltage range to 6.0V). This device has been developed for advanced, low power applications such as personal communications or data acquisition. The 24LC32 features an input cache for fast write loads with a capacity of eight 8-byte pages, or 64 bytes. It also features a fixed 4K-bit block of ultra-high endurance memory for data that changes frequently. The 24LC32 is capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to eight 24LC32 devices on the same bus, for to 256K bits address space. Advanced CMOS technology and broad voltage range make this device ideal for low-power/low voltage, nonvolatile code and data applications. The 24LC32 is available the standard 8-pin in plastic DIP and 8-pin surface mount SOIC package.I/O CONTROL LOGIC MEMORY CONTROL LOGIC XDEC EEPROM ARRAY PAGE LATCHES
is a trademark of Philips Corporation. Smart Serial is a trademark of Microchip Technology Inc.
Function User Configurable Chip Selects Ground Serial Address/Data I/O Serial Clock to 6.0V Power Supply No Internal Connection
VCC..................................................................................7.0V All inputs and outputs w.r.t. VSS............... -0.6V to VCC +1.0V Storage to +150�C Ambient temp. with power to +125�C Soldering temperature of leads (10 seconds)............. +300�C ESD protection on all pins.................................................. 4 kV
*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
VCC to 6.0V Commercial (C): Tamb Industrial (I): Tamb Parameter Symbol Min Max Units to +85�C Conditions
A1, A2, SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmitt Trigger inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby currentVIH VIL VHYS VOL ILI ILO CIN, COUT ICC Write ICC Read ICCS
Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF
(Note1) After this period the first clock pulse is generated Only relevant for repeated START condition
Output fall time from VIH min to VIL max Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance High Endurance Block Rest of Array(Note 2) Time the bus must be free before a new transmission can start (Note 100 pF (Note 3)
ms/page (Note 4) cycles 25�C, Vcc = 5.0V, Block Mode (Note 5)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation. 4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write cache for total time. 5: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained from our website.TF THIGH TLOW SCL TSU:STA THD:STA SDA IN TSP TAA SDA OUT TAA THD:DAT TSU:DAT TSU:STO