24LC62-ST Datasheet

1k/2k Software Addressable i 2 C Serial EePROM


Features, Applications

Software Write Protection Entire Array Lower Half

Low power CMOS technology 1 mA active current typical 10 �A standby current typical at 5.5V Software addressability allows to 255 devices on the same bus 2-wire serial interface bus, I2C compatible Automatic bus arbitration Wakes up to control code 0110 General purpose output pin can be used to enable other circuitry 100 kHz and 400 kHz compatibility Page-write buffer for to 16 bytes 10 ms max write cycle time for byte or page write 10,000,000 erase/write cycles guaranteed 8-pin PDIP, SOIC or TSSOP packages Temperature ranges supported: - Commercial (C): +70�C - Industrial (I): to +85�C


The Microchip Technology Inc. a 1K/2K bit Serial EEPROM developed for applications that require many devices on the same bus but do not have the I/O pins required to address each one individually. These devices contain an 8 bit address register that is set upon power-up and allows the connection to 255 devices on the same bus. When the process of assigning ID values to each device is in progress, the device will automatically handle bus arbitration if more than one device is operating on the bus. In addition, an external open drain output pin is available that can be used to enable other circuitry associated with each individual system. Low current design permits operation with typical standby and active currents of only 10 �A and 1 mA respectively. The device has a pagewrite capability for to 16 bytes of data. The device is available in the standard 8-pin PDIP, SOIC (150 mil), and TSSOP packages.

Function Ground Serial Data Serial Clock to 5.5V Power Supply No Internal Connection External Device Select Output

VCC........................................................................7.0V All inputs and outputs w.r.t. VSS......-0.6V to VCC +1.0V Storage temperature.......................... to +150�C Ambient temp. with power applied...... to +125�C Soldering temperature of leads (10 seconds).. +300�C ESD protection on all pins..................................... 4 kV

*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

VCC to +5.5V Commercial (C): Industrial (I): Symbol VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Write ICC Read ICCS -10 0.05 VCC Min. 0.7 VCC.3 VCC Tamb to +70�C Tamb +85 �C Max. Units mA �A IOL = 12 mA, VCC = 4.5V IOL = 8 mA, VCC = 2.5V VIN = Vss or Vcc VOUT = Vss or Vcc VCC = 5.0V (Note) Tamb = 25 �C, = 1 MHz VCC = 5.5V VCC = 5.5V, SCL = 400 kHz VCC = 5.5V, SDA = SCL = VCC Conditions

All parameters apply across the specified operating ranges unless otherwise noted. Parameter SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage (SDA and EDS pins) Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current

Note: This parameter is periodically sampled and not 100% tested.

Vcc to 5.5V Commercial (C): Industrial (I): Tamb to +70�C Tamb +85 �C Remarks All parameters apply across the specified operating ranges unless otherwise noted.

Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time


From VIL to VIH (Note 1) From VIL to VIH (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2)

Output fall time (from 0.7 VCC to 0.3 VCC) Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance

(Note 2) Time the bus must be free before a new transmission can start (Note 100 pF (Notes 1, 3)
ms Byte or Page mode cycles 25�C, VCC = 5.0V, Block Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.



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