28C64A-25I Datasheet

Note:this Product Has Become 'Obsolete' And is no Longer Offered as a Viable Device For Design


Features, Applications

Fast Read Access Time--150 ns CMOS Technology for Low Power Dissipation 30 mA Active 100 �A Standby Fast Byte Write or 1 ms Data Retention >200 years High Endurance - Minimum 100,000 Erase/Write Cycles Automatic Write Operation - Internal Control Timer - Auto-Clear Before Write Operation - On-Chip Address and Data Latches Data Polling Ready/Busy Chip Clear Operation Enhanced Data Protection - VCC Detector - Pulse Filter - Write Inhibit Electronic Signature for Device Identification 5-Volt-Only Operation Organized 8Kx8 JEDEC Standard Pinout - 28-pin Dual-In-Line Package - 32-pin PLCC Package - 28-pin SOIC Package Available for Extended Temperature Ranges: - Commercial: +70�C - Industrial: to +85�C

Data Protection Circuitry Chip Enable/ Output Enable Control Logic

The Microchip Technology Inc. is a CMOS 64K nonvolatile electrically Erasable PROM. The 28C64A is accessed like a static RAM for the read or write cycles without the need of external components. During a "byte write", the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of write cycle, the device will to a busy state and automatically clear and write the latched data using an internal control timer. To determine when the write cycle is complete, the user has a choice of monitoring the Ready/ Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in wiredor systems. Alternatively, Data polling allows the user to read the location last written to when the write operation is complete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reliability are required. A complete family of packages is offered to provide the utmost flexibility in applications.

Function Address Inputs Chip Enable Output Enable Wr ite Enable Data Inputs/Outputs Ready/Busy +5V Power Supply Ground No Connect ; No Inter nal Connection Not Used ; No Exter nal Connection is All owed

VCC and input voltagesw.r.t. V SS....... + 6.25V Voltage on OE w.r.t. VSS..................... to +13.5V Voltage A9w.r.t. V SS...................... Output Voltage w.r.t. V CC+0.6V Storage temperatur e......................... to +125�C Ambient temp. with power applied........ to +95�C

*Notice: Stresses ab ove those listed unde r "Maxi mum Ratings" may cause pe r manent damage to the e dvice. This is a stress rating only and functional ope ration of the device at those a ny other conditions ab ove those indicated in the ope ration listings of this specification is not implied. Exposure to maxi mum r ating conditions for extended pe r iods may affect device reliabilit y.

VCC +5V �10% Commercial (C): Tamb to +70�C Industr ial (I): Tamb to +85�C

Parameter Input Voltages Input Leakage Input Capacitance Output Voltages Output Leakage Output Capacitance Power Supply Current, Acti ve Power Supply Current, Standby

Status Logic `1' Logic `0' Logic `1' Logic `0' TTL input

VIN -0.1V to Vcc = 0V; Tamb = 1 MHz (Note 2) IOH -400 �A IOL 2.1 mA VOUT -0.1V to Vcc = 0V; Tamb = 1 MHz (Note = 5 MHz (Note 1) VCC CC-0.3 to Vcc WE = Vcc All other inputs equal CC or VSS

Note 1: AC power supply current above 2mA/MHz. 2: Not 100% tested.
AC Testing Waveform: Output Load: Input Rise and Fall Times: Ambient Temperature:

VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL 0.8V 1 TTL Load 20 ns Commercial (C): Tamb to +70�C Industrial (I): Tamb to +85�C

Parameter Address to Output Delay CE to Output Delay OE to Output Delay or OE High to Output Float Output Hold from Address, CE or OE, whichever occurs first. Endurance

Note 1: Not 100% tested. 2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

VIH OE VIL VOH Data VOL t ACC VIH WE VIL Notes: (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed CE - tOE after the falling edge of CE without impact on tCE (3) This parameter is sampled and is not 100% tested t OE(2) High t OH Valid Output High Z



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