28C64AT-25ITS Datasheet

64k ( 8k X 8 ) CMOS EePROM


Features, Applications

Fast Read Access Time--150 ns CMOS Technology for Low Power Dissipation 30 mA Active 100 �A Standby Fast Byte Write or 1 ms Data Retention >200 years High Endurance - Minimum 100,000 Erase/Write Cycles Automatic Write Operation - Internal Control Timer - Auto-Clear Before Write Operation - On-Chip Address and Data Latches Data Polling Ready/Busy Chip Clear Operation Enhanced Data Protection - VCC Detector - Pulse Filter - Write Inhibit Electronic Signature for Device Identification 5-Volt-Only Operation Organized 8Kx8 JEDEC Standard Pinout - 28-pin Dual-In-Line Package - 32-pin PLCC Package - 28-pin Thin Small Outline Package (TSOP) - 28-pin Very Small Outline Package (VSOP) 8x13.4mm Available for Extended Temperature Ranges: - Commercial: to +70�C


The Microchip Technology Inc. is a CMOS 64K nonvolatile electrically Erasable PROM. The 28C64A is accessed like a static RAM for the read or write cycles without the need of external components. During a "byte write", the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of write cycle, the device will to a busy state and automatically clear and write the latched data using an internal control timer. To determine when the write cycle is complete, the user has a choice of monitoring the Ready/ Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in wiredor systems. Alternatively, Data polling allows the user to read the location last written to when the write operation is complete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reliability are required. A complete family of packages is offered to provide the utmost flexibility in applications

Data Protection Circuitry Chip Enable/ Output Enable Control Logic

Function Address Inputs Chip Enable Output Enable Write Enable Data Inputs/Outputs Ready/Busy +5V Power Supply Ground No Connect; No Internal Connection Not Used; No External Connection is Allowed

VCC and input voltages w.r.t. VSS....... + 6.25V Voltage on OE w.r.t. VSS..................... to +13.5V Voltage on A9 w.r.t. VSS...................... to +13.5V Output Voltage w.r.t. VSS................ to VCC+0.6V Storage temperature.......................... to +125�C Ambient temp. with power applied....... to +95�C

*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

VCC +5V �10% Commercial (C): Tamb to +70�C Industrial (I): Tamb to +85�C

Parameter Input Voltages Input Leakage Input Capacitance Output Voltages Output Leakage Output Capacitance Power Supply Current, Active Power Supply Current, Standby

Status Logic `1' Logic `0' Logic `1' Logic `0' TTL input

VIN -0.1V to Vcc +1 VIN = 0V; Tamb = 1 MHz (Note 2) IOH -400 �A IOL 2.1 mA VOUT -0.1V to Vcc +0.1V VIN = 0V; Tamb = 1 MHz (Note = 5 MHz (Note 1) VCC CE = VIH CE = VIH VCC-0.3 to Vcc +1

Note 1: AC power supply current above 2mA/MHz. 2: Not 100% tested.
AC Testing Waveform: Output Load: Input Rise and Fall Times: Ambient Temperature:

VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL 0.8V 1 TTL Load 20 ns Commercial (C): Tamb to +70�C Industrial (I): Tamb to +85�C

Parameter Address to Output Delay CE to Output Delay OE to Output Delay or OE High to Output Float Output Hold from Address, CE or OE, whichever occurs first. Endurance

Note 1: Not 100% tested. 2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

VIH OE VIL VOH Data VOL t ACC VIH WE VIL Notes: (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed t OE after the falling edge of CE without impact on tCE (3) This parameter is sampled and is not 100% tested t OE(2) High t OH Valid Output High Z



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