Homedatasheet28F008SA-L200

28F008SA-L200 Datasheet

Intel Flashfile Memory28F008SA (x8)
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Description

Features, Applications

High-Density Symmetrically-Blocked Architecture Sixteen 64-Kbyte Blocks Extended Cycling Capability 100,000 Block Erase Cycles 1.6 Million Block Erase Cycles per Chip Automated Byte Write and Block Erase Command User Interface Status Register System Performance Enhancements RY/BY# Status Output Erase Suspend Capability

Deep Power-Down Mode 0.20 �A ICC Typical Very High-Performance Read 85 ns Maximum Access Time SRAM-Compatible Write Interface Hardware Data Protection Feature Erase/Write Lockout during Power Transitions Industry Standard Packaging 40-Lead TSOP, 44-Lead PSOP ETOXTM V Nonvolatile Flash Technology 12 V Byte Write/Block Erase

The 5 Volt FlashFileTM memory 28F008SA's extended cycling, symmetrically blocked architecture, fast access time, write automation and low power consumption provide a more reliable, lower power, lighter weight and higher performance alternative to traditional rotating disk technology. The 28F008SA brings new capabilities to portable computing. Application and operating system software stored in resident flash memory arrays provide instant-on, rapid eXecute-In-Place (XIP) and protection from obsolescence through in-system software updates. Resident software also extends system battery life and increases reliability by reducing disk drive accesses. For high-density data acquisition applications, the 28F008SA offers a more cost-effective and reliable alternative to SRAM and battery. Traditional high-density embedded applications, such as telecommunications, can take advantage of the 28F008SA's nonvolatility, blocking and minimal system code requirements for flexible firmware and modular software designs. The 28F008SA is offered in 40-lead TSOP and 44-lead PSOP packages. Pin assignments simplify board layout when integrating multiple devices in a flash memory array or subsystem. This device uses an integrated Command User Interface and state machine for simplified block erasure and byte write. The 28F008SA memory map consists of 16 separately erasable 64-Kbyte blocks. Intel� 28F008SA employs advanced CMOS circuitry for systems requiring low power consumption and noise immunity. Its 85 ns access time provides superior performance when compared with magnetic storage media. A deep power-down mode lowers power consumption 1 �W typical through VCC, crucial in portable computing, handheld instrumentation and other low-power applications. The RP# power control input also provides absolute data protection during system power-up/down. Manufactured on Intel� 0.4 micron ETOX V process technology, the 28F008SA provides the highest levels of quality, reliability and cost-effectiveness. NOTE: This document formerly known x 8) FlashFileTM Memory.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F008SA may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, 80217-9808 or call 1-800-548-4725 or visit Intel's website at http://www.intel.com

*Third-party brands and names are the property of their respective owners

PAGE 8.0 DESIGN CONSIDERATIONS........................ 17 8.1 Three-Line Output Control.......................... 17 8.2 RY/BY# and Byte Write/Block Erase Polling....................................................... 17 8.3 Power Supply Decoupling.......................... 17 8.4 VPP Trace on Printed Circuit Boards.......... 22 8.5 VCC, VPP, RP# Transitions and the Command/Status Registers...................... 22 8.6 Power Up/Down Protection........................ 22 8.7 Power Dissipation...................................... 22 9.0 ELECTRICAL SPECIFICATIONS................. 23 9.1 Absolute Maximum Ratings....................... 23 9.2 Operating Conditions................................. 23 9.3 Capacitance............................................... 9.4 DC Characteristics..................................... 24 9.5 Extended Temperature Operating Conditions................................................. 9.6 DC Characteristics--Extended Temperature Operation.................................................. 9.7 AC Characteristics--Read-Only Operations................................................ 9.8 AC Characteristics--Read-Only Operations-- Extended Temperature Operation.................................................. 9.9 AC Characteristics--Write Operations....... 33 9.10 Block Erase and Byte Write Performance 9.11 AC Characteristics--Write Operations-- Extended Temperature Operation............. 35 9.12 Block Erase and Byte Write Performance-- Extended Temperature Operation............. 36 9.13 Alternative CE#-Controlled Writes............ 38 9.14 Alternative CE#-Controlled Writes-- Extended Temperature Operation............. 40 10.0 ORDERING INFORMATION....................... 42 11.0 ADDITIONAL INFORMATION..................... 42

1.0 PRODUCT OVERVIEW.................................. 5 2.0 PRINCIPLES OF OPERATION..................... 10 2.1 Command User Interface and Write Automation............................................... 11 2.2 Data Protection.......................................... 11 3.0 BUS OPERATION........................................ 11 3.1 Read.......................................................... 11 3.2 Output Disable........................................... 11 3.3 Standby..................................................... 11 3.4 Deep Power-Down..................................... 12 3.5 Intelligent Identifier Operation.................... 12 3.6 Write.......................................................... 13 4.0 COMMAND DEFINITIONS............................ 13 4.1Read Array Command................................ 13 4.2 Intelligent Identifier Command................... 15 4.3 Read Status Register Command............... 15 4.4 Clear Status Register Command............... 15 4.5 Erase Setup/Erase Confirm Commands.... 15 4.6 Erase Suspend/Erase Resume Commands15 4.7 Byte Write Setup/Write Commands.......... 16 5.0 EXTENDED BLOCK ERASE/BYTE WRITE CYCLING..................................................... 16 6.0 AUTOMATED BYTE WRITE......................... 16 7.0 AUTOMATED BLOCK ERASE..................... 16


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