to 3.6V Supply Read Access Time--300 ns CMOS Technology for Low Power Dissipation 8 mA Active 50 �A CMOS Standby Current Byte Write Time--3 ms Data Retention >200 years High Endurance - Minimum 100,000 Erase/Write Cycles Automatic Write Operation - Internal Control Timer - Auto-Clear Before Write Operation - On-Chip Address and Data Latches Data Polling Ready/Busy Chip Clear Operation Enhanced Data Protection - VCC Detector - Pulse Filter - Write Inhibit Electronic Signature for Device Identification Organized 8Kx8 JEDEC Standard Pinout - 28-pin Dual-In-Line Package - 32-pin Chip Carrier (Leadless or Plastic) Available for Extended Temperature Ranges: - Commercial: +70�C - Industrial: to +85�C
I/O0...................I/O7 VSS VCC OE WE Rdy/ Busy A0 A12 Data Protection Circuitry Chip Enable/ Output Enable Control Logic Auto Erase/Write Timing Program Voltage Generation Y Decoder Data Poll Input/Output BuffersDESCRIPTION
The Microchip Technology Inc. is a CMOS 64K non-volatile electrically Erasable PROM organized as 8K words by 8 bits. The 28LV64A is accessed like a static RAM for the read or write cycles without the need of external components. During a "byte write", the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of write cycle, the device will to a busy state and automatically clear and write the latched data using an internal control timer. To determine when the write cycle is complete, the user has a choice of monitoring the Ready/Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in `wired-or' systems. Alternatively, Data polling allows the user to read the location last written to when the write operation is complete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reliability are required. A complete family of packages is offered to provide the utmost flexibility in applications.
Name - I/O7 RDY/Busy VCC VSS NC NU Chip Enable Output Enable Write Enable Data Inputs/Outputs Ready/Busy + Power Supply Ground No Connect; No Internal Connection Not Used; No External Connection is Allowed
VCC and input voltages w.r.t. VSS...... + 6.25V Voltage on OE w.r.t. VSS...................... to +13.5V Voltage on A9 w.r.t. VSS...................... to +13.5V Output Voltage w.r.t. VSS............... to VCC+0.6V Storage to +150�C Ambient temp. with power to +125�C
*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.VCC to 3.6V Commercial (C): Tamb to 70�C Industrial (I): Tamb to 85�C
Parameter Input Voltages Input Leakage Input Capacitance Output Voltages
Status Logic "1" Logic "2" Logic "1" Logic "0" TTL input
Output Leakage Output Capacitance Power Supply Current, Activity
TTL input ICC(S)TTL TTL input ICC(S)TTL CMOS input ICC(S)CMOS
VIN to VCC+1 Vin = 0V; Tamb = 1 MHz (Note 1) IOH = -100�A IOL 2.0 mA for RDY/Busy VOUT to VCC+0.1V VOUT = 0V; Tamb = 1 MHz (Note = 5 MHz (Note IO = OmA VCC CE = VIL CE = VIH CE = VIH CE = VCC WE = VCC All other inputs equal VCC or VSSNote 1: Not 100% tested. 2: AC power supply current above 5 MHz: 2 mA/Mhz.
AC Testing Waveform: Output Load: Input Rise and Fall Times: Ambient Temperature:
Parameter Address to Output Delay CE to Output Delay OE to Output Delay or OE High to Output Float Output Hold from Address, CE or OE, whichever occurs first. Sym Min
VIH = 2.0V; VIL = 0.6V; VOH = VOL VCC/2 1 TTL Load 20 ns Commercial (C): Tamb to +70�C Industrial (I) : Tamb to +85�C
Note 1: Not 100% tested. 2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
VIH OE VIL VOH Data VOL t ACC VIH WE VIL Notes: (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed t OE after the falling edge of CE without impact on tCE (3) This parameter is sampled and is not 100% tested t OE(2) High t OH Valid Output High Z