|GeodeTM GXm Processor Integrated x86 Solution with MMX Support
The National Semiconductor� GeodeTM GXm processor is an advanced 32-bit x86 compatible processor offering high performance, fully accelerated 2D graphics, a 64-bit synchronous DRAM controller and a PCI bus controller, all on a single chip that is compatible with Intel's MMX technology. The GXm processor core is a proven design that offers competitive CPU performance. It has integer and floating point execution units that are based on sixth-generation technology. The integer core contains a single, six-stage execution pipeline and offers advanced features such as operand forwarding, branch target buffers, and extensive write buffering. 16 KB write-back L1 cache is accessed in a unique fashion that eliminates pipeline stalls to fetch operands that hit in the cache. In addition to the advanced CPU features, the GXm processor integrates a host of functions which are typically implemented with external components. A full-function graphics accelerator provides pixel processing and rendering functions. A separate on-chip video buffer enables >30 fps MPEG1 video playback when used together with the CS5530 I/O companion chip. Graphics and system memory accesses are supported by a tightly-coupled synchronous DRAM (SDRAM) memory controller. This tightly coupled memory subsystem eliminates the need for an external L2 cache. The GXm processor includes Virtual System Architecture� (VSATM technology) enabling XpressGRAPHICS and XpressAUDIO subsystems as well as generic emulation capabilities. Software handler routines for the XpressGRAPHICS and XpressAUDIO subsystems can be included in the BIOS and provide compatible VGA and 16bit industry standard audio emulation. XpressAUDIO technology eliminates much of the hardware traditionally associated with audio functions.
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation. Geode and VSA are trademarks of National Semiconductor Corporation. For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.Features
Packaged in: 352-Terminal Ball Grid Array (BGA) or 320-Pin Staggered Pin Grid Array (SPGA) 0.35-micron four layer metal CMOS process Split rail design (3.3V I/O and 2.9V core)
Graphics pipeline performance significantly increased over previous generations by pipelining burst reads/writes Accelerates BitBLTs, line draw, text Supports all 256 raster operations Supports transparent BLTs Runs at core clock frequency Full VGA and VESA mode support Special "Driver level" instructions utilize internal scratchpad for enhanced performance
Supports the MMX instruction set extension for the acceleration of multimedia applications Speeds offered to 266 MHz 16 KB unified L1 cache Integrated Floating Point Unit (FPU) Re-entrant System Management Mode (SMM) enhanced for VSA
Video Generator (VG) improves memory efficiency for display refresh with SDRAM Supports a separate MPEG1 video buffer and data path to enable video acceleration in the CS5530 Internal palette RAM for use with the CS5530 Direct interface to CS5530 for CRT and TFT flat panel support which eliminates need for external RAMDAC Hardware frame buffer compressor/decompressor Hardware cursor Supports to 1280x1024x8 bpp and 1024x768x16 bpp
Fixed, rotating, hybrid, or ping-pong arbitration Supports up to three PCI bus masters Synchronous CPU and PCI bus clock frequency Supports concurrency between PCI master and L1 cache
Designed to support CS5530 power management architecture CPU only Suspend or full 3V Suspend supported: Clocks to CPU core stopped for CPU Suspend All on-chip clocks stopped for 3V Suspend refresh supported for 3V Suspend
Memory control/interface directly from CPU 64-Bit wide memory bus Support for: Two 168-pin unbuffered DIMMs to 16 open banks simultaneously Single or 16-byte reads (burst length of two)
Architecture allows OS independent (software) virtualization of hardware functions Provides compatible high performance legacy VGA core functionality Note: GUI (Graphical User Interface) graphics acceleration is pure hardware.
INTEGER UNIT. 8 FLOATING POINT UNIT. 9 WRITE-BACK CACHE UNIT. 9 MEMORY MANAGEMENT UNIT. 9 1.4.1 Internal Bus Interface Unit. 9 INTEGRATED FUNCTIONS. 9 1.5.1 Graphics Accelerator. 9 1.5.2 Display Controller. 10 1.5.3 XpressRAM Memory Subsystem. 10 1.5.4 PCI Controller. 10 GEODE GXM/CS5530 SYSTEM DESIGNS. 11
2.1 2.2 PIN ASSIGNMENTS. SIGNAL DESCRIPTIONS. 2.2.1 System Interface Signals. 2.2.2 PCI Interface Signals. 2.2.3 Memory Controller Interface Signals. 2.2.4 Video Interface Signals. 2.2.5 Power, Ground, and No Connect Signals. 2.2.6 Internal Test and Measurement Signals. SUBSYSTEM SIGNAL CONNECTIONS. POWER PLANES.
3.2 3.3 CORE PROCESSOR INITIALIZATION. INSTRUCTION SET OVERVIEW. 3.2.1 Lock Prefix. REGISTER SETS. 3.3.1 Application Register Set. 3.3.2 System Register Set. 3.3.3 Model Specific Register Set. 3.3.4 Time Stamp Counter. ADDRESS SPACES. 3.4.1 I/O Address Space. 3.4.2 Memory Address Space. OFFSET, SEGMENT, AND PAGING MECHANISMS. OFFSET MECHANISM. DESCRIPTORS AND SEGMENT MECHANISMS. 3.7.1 Real and Virtual 8086 Mode Segment Mechanisms. 3.7.2 Segment Mechanism in Protective Mode. 3.7.3 GDTR and LDTR Registers. 3.7.4 Descriptor Bit Structure. 3.7.5 Gate Descriptors. MULTITASKING AND TASK STATE SEGMENTS. PAGING MECHANISM.