|54AC373 54ACT373 Octal Transparent Latch with TRI-STATE Outputs
54AC373 54ACT373 Octal Transparent Latch with TRI-STATE � Outputs
The 'AC/'ACT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.Features
ICC and IOZ reduced by 50% Eight latches in a single package TRI-STATE outputs for bus interfacing Outputs source/sink mA 'ACT373 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) 'ACT373: 5962-87556Description Data Inputs Latch Enable Input Output Enable Input TRI-STATE Latch Outputs
TRI-STATE is a registered trademark of National Semiconductor Corporation. FACT is a registered trademark of Fairchild Semiconductor Corporation.
The 'AC/'ACT373 contains eight D-type latches with TRI-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH to Low transition of Latch Enable
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.