54ACTQ373DM-MLS Datasheet

Military/Aerospace->FACT ACQ


Features, Applications
54ACQQ373 54ACTQ373 Quiet Series Octal Transparent Latch with TRI-STATE Outputs
54ACQ373 54ACTQ373 Quiet Series Octal Transparent Latch with TRI-STATE � Outputs

The 'ACQ/'ACTQ373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. The 'ACQ/'ACTQ373 utilizes NSC Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet SeriesTM features GTOTM output control and undershoot corrector in addition to a split ground bus for superior performance.


n ICC and IOZ reduced 50% n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch up immunity n Eight latches in a single package n TRI-STATE outputs drive bus lines or buffer memory address registers n Outputs source/sink mA n Faster prop delays than the standard 4 kV minimum ESD immunity ('ACQ) n Standard Military Drawing (SMD) 'ACQ373: 5962-92178

Description Latch Enable Input Output Enable Input TRI-STATE Latch Outputs

GTOTM is a trademark of National Semiconductor Corporation. TRI-STATE is a registered trademark of National Semiconductor Corporation. FACT is a registered trademark of Fairchild Semiconductor Corporation. FACT Quiet SeriesTM is a trademark of Fairchild Semiconductor Corporation.

The 'ACQ/'ACTQ373 contains eight D-type latches with TRI-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.

H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH to Low transition of Latch Enable

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = VCC 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = VCC 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latchup Source or Sink Current Junction Temperature (TJ) CDIP -0.5V to VCC -0.5V to VCC + 0.5V

Supply Voltage (VCC) 'ACQ 'ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACQ/ACTQ Minimum Input Edge Rate V/t 'ACQ Devices VIN from 70% of VCC 4.5V, 5.5V Minimum Input Edge Rate V/t 'ACTQ Devices VIN from to 2.0V VCC 0V to VCC 0V to VCC to +125�C

Note: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from to +125�C. Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT � circuits outside databook specifications.

Symbol Parameter VCC (V) VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage to +125�C Guaranteed Limits (Note 2) VIN = VIL or VIH IOH mA V IOH -24 mA IOH -24 mA IOUT �A V IOUT �A V VOUT 0.1V or VCC 0.1V V VOUT 0.1V or VCC - 0.1V Units Conditions



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