5962-8607201FA Datasheet



Features, Applications

The is a fully synchronous 4-stage up down counter The a modulo-16 binary counter Features a preset capability for programmable operation carry lookahead for easy cascading and U D input to control the direction of counting All state changes whether in counting or parallel loading are initiated by the LOW-to-HIGH transition of the clock


Asynchronous counting and loading Built-in lookahead carry capability Presettable for programmable operation

Package Description (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line (0 150 Wide) Molded Small Outline JEDEC (0 300 Wide) Molded Small Outline EIAJ

Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB

TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation

Count Enable Parallel Input (Active LOW) Count Enable Trickle Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Parallel Enable Input (Active LOW) Up-Down Count Control Input Flip-Flop Outputs Terminal Count Output (Active LOW)

The 'F169 uses edge-triggered J-K type flip-flops and has no constraints on changing the control or data input signals in either state of the clock The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter The parallel load operation takes precedence over other operations as indicated in the Mode Select Table When PE is LOW the data on the � P3 inputs enters the flip-flops on the next rising edge of the clock In order for counting to occur both CEP and CET must be LOW and PE must be HIGH the U D input then determines the direction of counting The Terminal Count (TC) output is normally HIGH and goes LOW provided that CET is LOW when a counter reaches zero in the Count Down mode or reaches 15 for the 'F169 in the Count Up mode The TC output state is not a function of the Count Enable Parallel (CEP) input level Since the TC signal is derived by decoding the flip-flop states there exists the possibility of decoding spikes on TC For this reason the use as a clock signal is not recommended (see logic equations below) 1) Count Enable e CEP CET Q2 Q3 (Up) CET 3) Down Q2 Q3 (Down) CET

Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays

Mode Select Table PE CEP CET Action on Rising Clock Edge Load (Pn x Qn) Count Up (Increment) Count Down (Decrement) No Change (Hold) No Change (Hold)

H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial



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