The is a high-speed 1-of-8 decoder/ demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion a 1-of-24 decoder using just three 'AC/'ACT138 devices a 1-of-32 decoder using four 'AC/'ACT138 devices and one inverter.Features
ICC reduced by 50% Demultiplexing capability Multiple input enable for easy expansion Active LOW mutually exclusive outputs Outputs source/sink mA 'ACT138 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) 'ACT138: 5962-87554Description Address Inputs Enable Inputs Enable Input Outputs
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The 'AC/'ACT138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted inputs A1, A2) and, when enabled, provides eight mutually exclusive active-LOW outputs (O0�O7). The 'AC/'ACT138 features three Enable inputs, two active-LOW (E1, E2) and one active-HIGH (E3). All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device 1-of-32 (5 lines to 32 lines) decoder with just four 'AC/'ACT138 devices and one inverter (see Figure 1). The 'AC/'ACT138 can be used an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not used must be permanently tied to their appropriate active-HIGH or active-LOW state.H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.