Improved versions of the UC3823/UC3825 PWMs Compatible with Voltage or Current-Mode Topologies Practical Operation at Switching Frequencies 1MHz 50ns Propagation Delay to Output High Current Dual Totem Pole Outputs (2A Peak) Trimmed Oscillator Discharge Current Low 100�A Startup Current Pulse-by-Pulse Current Limiting Comparator Latched Overcurrent Comparator With Full Cycle RestartDESCRIPTION
The & B and the & B family of PWM control ICs are improved versions of the standard & UC3825 family. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12MHz while input offset voltage is 2mV. Current limit threshold is guaranteed to a tolerance of 5%. Oscillator discharge current is specified at 10mA for accurate dead time control. Frequency accuracy is improved to 6%. Startup supply current, typically 100�A, is ideal for off-line applications. The output drivers are redesigned to actively sink current during UVLO at no expense to the startup current specification. In addition each output is capable of 2A peak currents during transitions. Functional improvements have also been implemented in this family. The UC3825 shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2V. The overcurrent comparator sets a latch that ensures full discharge of the soft start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state. In the event of continuous faults, the soft start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period. The UC3825 Clock pin has become CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing. (continued)
The UC3825A,B has dual alternating outputs and the same pin configuration of the UC3825. The UC3823A,B outputs operate in phase with duty cycles from zero to less than 100%. The pin configuration of the UC3823A,B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the current limit comparator. "A" version parts have UVLO thresholds identical to the original UC3823/25. The "B" versions have UVLO thresholds of 16 and 10V, intended for ease of use in off-line applications. Consult Application Note U-128 for detailed technical and applications information. Contact the factory for further packaging and availability information.
Supply Voltage (VC, VCC). 22V Output Current, Source or Sink (Pins OUTA, OUTB) DC. 0.5A Pulse (0.5�s). 2.2A Power Ground (PGND). �0.2V Analog Inputs (INV, NI, RAMP). to 7V (ILIM, SS). to 6V Clock Output Current (CLK/LEB). �5mA Error Amplifier Output Current (EAOUT). 5mA Soft Start Sink Current (SS). 20mA Oscillator Charging Current (RT). �5mA Power Dissipation 60�C. 1W Storage Temperature Range. to +150�C Junction Temperature. to +150�C Lead Temperature (Soldering, 10 sec.). 300�C
All currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.DIL-16, SOIC-16, (Top View) or N Package; DW Package PLCC-20, LCC-20, (Top View) Q, L Packages
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for to +125�C for the UC1823A,B and to +85�C for the UC2823A,B and to +70�C for the UC3823A,B and = 1nF, VCC TA = TJ.
PARAMETER Reference Section Output Voltage Line Regulation Load Regulation Total Output Variation Temperature Stability Output Noise Voltage Long Term Stability Short Circuit Current 12 < VCC < 10mA Line, Load, Temp TMIN TA < TMAX (Note < 10kHz (Note 125�C, 1000 hours (Note 1) VREF mV V mV/�C �VRMS mV mA TEST CONDITIONS MIN TYP MAX UNITS
UC2823A,B/2825A,B UC3823A,B/3825A,B ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for to +125�C for the UC1823A,B and to +85�C for the UC2823A,B and to +70�C for the UC3823A,B and = 1nF, VCC TA = TJ.
PARAMETER Oscillator Section Initial Accuracy Total Variation Voltage Stability Temperature Stability Initial Accuracy Total Variation Clock Out High Clock Out Low Ramp Peak Ramp Valley Ramp Valley to Peak Oscillator Discharge Current Error Amplifier Section Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain CMRR PSRR Output Sink Current Output Source Current Output High Voltage Output Low Voltage Gain Bandwidth Product Slew Rate PWM Comparator RAMP Bias Current Minimum Duty Cycle Maximum Duty Cycle Leading Edge Blanking LEB Resistor EAOUT Zero D.C. Threshold Delay to Output Current Limit/Start Sequence/Fault Section Soft Start Charge Current Full Soft Start Threshold Restart Discharge Current Restart Threshold ILIM Bias Current Limit Threshold 0 < VILIM 0.95 1 VSS = 2.5V VSS = 470pF VCLK/LEB = 3V VRAMP = 0V VEAOUT = 2.1V, VRAMP to 2V Step (Note VRAMP % ns kohm 1.5V < VCM 12V < VCC < 20V VEAOUT = 1V VEAOUT = 4V IEAOUT = �0.5mA IEAOUT = 200kHz (Note mA V MHz V/�s RT = Open, VCT = 25�C (Note 1) Line, Temperature (Note 12V < VCC < 20V TMIN TA < TMAX (Note = 25�C (Note = 220pF (Note kHz % MHz mA TEST CONDITIONS MIN TYP MAX UNITS