The is an enhanced version of the industry standard 8237A Direct Memory Access (DMA) controller, fabricated using Intersil's advanced 2 micron CMOS process. Pin compatible with NMOS designs, the 82C37A offers increased functionality, improved performance, and dramatically reduced power consumption. The fully static design permits gated clock operation for even further reduction of power. The 82C37A controller can improve system performance by allowing external devices to transfer data directly to or from system memory. Memory-to-memory transfer capability is also provided, along with a memory block initialization feature. DMA requests may be generated by either hardware or software, and each channel is independently programmable with a variety of features for flexible operation. The 82C37A is designed to be used with an external address latch, such as the 82C82, to demultiplex the most significant 8-bits of address. The 82C37A can be used with industry standard microprocessors such NSC800, 80186 and others. Multimode programmability allows the user to select from three basic types of DMA services, and reconfiguration under program control is possible even with the clock to the controller stopped. Each channel has a full 64K address and word count range, and may be programmed to autoinitialize these registers following DMA termination (end of process).Features
Compatible with the NMOS 8237A Four Independent Maskable Channels with Autoinitialization Capability Cascadable to any Number of Channels High Speed Data Transfers: to 4MBytes/sec with 8MHz Clock to 6.25MBytes/sec with 12.5MHz Clock Memory-to-Memory Transfers Static CMOS Design Permits Low Power Operation - ICCSB = 10�A Maximum - ICCOP = 2mA/MHz Maximum Fully TTL/CMOS Compatible Internal Registers may be Read from Software
PART NUMBER MR82C37A-12/B 5962-9054303MXA SMD# 44 Pad CLCC SMD# 40 Ld CERDIP 44 Ld PLCC PACKAGE 40 Ld PDIP TEMPERATURE RANGE to +125oC PKG. NO. F40.6 J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com 407-727-9207 | Copyright � Intersil Corporation 1999IOR IOW MEMR MEMW NC READY HLDA ADSTB AEN HRQ CS CLK RESET DREQ1 DREQ0 (GND) VSS
EOP RESET CS READY CLK AEN ADSTB MEMR MEMW IOR IOW TIMING AND CONTROL DECREMENTOR TEMP WORD COUNT REG (16) 16-BIT BUS 16-BIT BUS READ BUFFER BASE ADDRESS (16) BASE WORD COUNT (16) READ WRITE BUFFER CURRENT ADDRESS (16) CURRENT WORD COUNT (16) OUTPUT BUFFER - A7 INC/DECREMENTOR TEMP ADDRESS REG (16) IO BUFFER - A3
SYMBOL VCC PIN NUMBER 31 TYPE DESCRIPTION VCC: is the +5V power supply pin. A 0.1�F capacitor between pins 31 and 20 is recommended for decoupling. Ground I CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A operations. This input may be driven from to 12.5MHz for the 82C37A-12, from to 8MHz for the 82C37A, or from to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for CPU communications. RESET: This is an active high input which clears the Command, Status, Request, and Temporary registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore requests. Following a Reset, the controller in an idle cycle. READY: This signal can be used to extend the memory read and write pulses from the 82C37A to accommodate slow memories or I/O devices. READY must not make transitions during its specified set-up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode. HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has relinquished control of the system busses. HLDA is a synchronous input and must not transition during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising edge of CLK, during which time HLDA must not transition. DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is programmable. RESET initializes these lines to active high. DREQ must be maintained until the corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set. DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus. The outputs are enabled in the Program condition during the I/O Read to output the contents of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the CPU is programming the 82C37A control registers. During DMA cycles, the most significant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB. In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write the data into the new memory location. I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, is an input control signal used by the CPU to read the control registers. In the Active cycle, is an output control signal used by the 82C37A to access data from the peripheral during a DMA Write transfer. I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, is an input control signal used by the CPU to load information into the 82C37A. In the Active cycle, is an output control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.