|TLC1543Q 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
10-Bit Resolution A/D Converter 11 Analog Input Channels Three Built-In Self-Test Modes Inherent Sample-and-Hold Function Total Unadjusted Error. � 1 LSB Max On-Chip System Clock End-of-Conversion (EOC) Output Terminal Compatible With TLC542 CMOS Technologydescription
The TLC1543C, TLC1543I, and TLC1543Q are CMOS 10-bit switched-capacitor successive-approximation analog-to-digital converters. These devices have three inputs and a 3-state output [chip select (CS), input-output clock (I/O CLOCK), address input (ADDRESS), and data output (DATA OUT)] that provide a direct 4-wire interface to the serial port of a host processor. These devices allow high-speed data transfers from the host. In addition to a high-speed A /D converter and versatile control capability, these devices have an on-chip 14-channel multiplexer that can select any one of 11 analog inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic. At the end A /D conversion, the end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated in the devices features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating free-air temperature range.
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PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.TLC1543Q 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (DB) TLC1542QDB TLC1543QDB SMALL OUTLINE (DW) TLC1542QDW TLC1543QDW CHIP CARRIER (FN) TLC1542QFN TLC1543QFN PLASTIC DIP (N) TLC1542MFK TLC1542MJ CHIP CARRIER (FK) CERAMIC DIP (J)
REF+ A10 14-Channel Analog Multiplexer Sample and Hold 10-Bit Analog-to-Digital Converter (switched capacitors) 10 REF � 134 3 Self-Test Reference ADDRESS 17 System Clock, Control Logic, and I/O Counters
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE 1 k TYP 60 pF TYP (equivalent input capacitance) INPUT CIRCUIT IMPEDANCE DURING HOLD MODE 5 M TYPTLC1543Q 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
TERMINAL NAME ADDRESS NO. 17 I/O I DESCRIPTION Serial address input. A 4-bit serial address selects the desired analog input or test voltage that to be converted next. The address data is presented with the MSB first and shifts in on the first four rising edges of I/O CLOCK. After the four address bits have been read into the address register, this input is ignored for the remainder of the current conversion period. Analog signal inputs. The 11 analog inputs are applied to these terminals and are internally multiplexed. The driving source impedance should be less than or equal 1 k. Chip select. A high-to-low transition on this input resets the internal counters and controls and enables DATA OUT, ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup time plus two falling edges of the internal system clock. The 3-state serial output for the A/D conversion result. This output is in the high-impedance state when CS is high and active when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The next falling edge of I/O CLOCK drives this output to the logic level corresponding to the next most significant bit, and the remaining bits shift out in order with the LSB appearing on the ninth falling edge of I/O CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial interface data transfers of more than ten clocks produce zeroes as the unused LSBs. End of conversion. This output goes from a high to a low logic level on the trailing edge of the tenth I/O CLOCK and remains low until the conversion is complete and data are ready for transfer. The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to this terminal. Input/output clock. This terminal receives the serial I/O CLOCK input and performs the following four functions: 1) It clocks the four input address bits into the address register on the first four rising edges of the I/O CLOCK with the multiplex address available after the fourth rising edge. 2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins charging the capacitor array and continues do so until the tenth falling edge of I/O CLOCK. 3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT. 4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock. The upper reference voltage value (nominally VCC) is applied to this terminal. The maximum input voltage range is determined by the difference between the voltage applied to this terminal and the voltage applied to the REF � terminal. The lower reference voltage value (nominally ground) is applied to this terminal. Positive supply voltage
With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state. The serial interface then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O CLOCK. During this transfer, the serial interface also receives the previous conversion result from DATA OUT. I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface. The first four I/O clocks load the address register with the 4-bit address on ADDRESS, selecting the desired analog channel, and the next six clocks providing the control timing for sampling the analog input.