High Performance Microprocessor with Memory Management and Protection
The Intersil is a static CMOS version of the NMOS 80286 microprocessor. The is an advanced, high-performance microprocessor with specially optimized capabilities for multiple user and multi-tasking systems. The 80C286/883 has built-in memory protection that supports operating system and task isolation as well as program and data privacy within tasks. The 80C286/883 includes memory management capabilities that map 230 (one gigabyte) of virtual address space per task into 224 bytes (16 megabytes) of physical memory. The 80C286/883 is upwardly compatible with 80C86 and 80C88 software (the 80C286/883 instruction set is a superset of the 80C86/80C88 instruction set). Using the 80C286/ 883 real address mode, the 80C286/883 is object code compatible with existing 80C86 and 80C88 software. In protected virtual address mode, the 80C286/883 is source code compatible with 80C86 and 80C88 software but may require upgrading to use virtual address as supported by the 80C286/883's integrated memory management and protection mechanism. Both modes operate at full 80C286/883 performance and execute a superset of the 80C86 and 80C88 instructions. The 80C286/883 provides special operations to support the efficient implementation and execution of operating systems. For example, one instruction can end execution of one task, save its state, switch to a new task, load its state, and start execution of the new task. The segment-not-present exception and restartable instructions.Features
This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. Compatible with NMOS 80286/883 Static CMOS Design for Low Power Operation - ICCSB = 5mA Maximum - ICCOP = 185mA Maximum (80C286-10/883) - ICCOP = 220mA Maximum (80C286-12/883) Large Address Space - 16 Megabytes Physical - 1 Gigabyte Virtual per Task Integrated Memory Management, Four-Level Memory Protection and Support for Virtual Memory and Operating Systems Two 80C86 Upward Compatible Operating Modes - 80C286/883 Real Address Mode - Protected Virtual Address Mode Compatible with 80287 Numeric Data Co-Processor
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com 407-727-9207 | Copyright � Intersil Corporation 1999
68 LEAD PGA, COMPONENT PAD VIEW As viewed from underside of the component when mounted on the board.ERROR NC INTR NMI PEREQ READY HLDA M/IO NC BUSY NC VSS VCC HOLD COD/INTA LOCK
P.C. BOARD VIEW As viewed from the component side of the P.C. board.
Supply Voltage. +8.0V Input, Output or I/O Voltage Applied. GND -1.0V to VCC +1.0V Storage Temperature Range. to +150oC Junction Temperature. +175oC Lead Temperature (Soldering 10s). +300oC ESD Classification. Class 1Thermal Resistance (Typical) JA JC PGA Package. 35oC/W 6oC/W Gate Count. 22,500 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.NOTE: JA is measured with the component mounted on an evaluation PC board in free air.
Operating Voltage Range. to +5.5V Operating Temperature Range. to +125oC System Clock (CLK) RISE Time (From 3.6V. 8ns (Max) System Clock (CLK) FALL Time (from 1.0V). 8ns (Max) Input RISE and FALL Time (From 80C286-10/883. 10ns (Max) 80C286-12/883. 8ns (Max)
PARAMETER Input LOW Voltage Input HIGH Voltage CLK Input LOW Voltage CLK Input HIGH Voltage Output LOW Voltage Output HIGH Voltage
VIN = GND or VCC, VCC = 5.5V, Pins VCC = 4.5V and 5.5V, VIN = 1.0V, Note 1 VCC = 4.5V and 5.5V, VIN = 3.0V, Note 2 VCC = 4.5V and 5.5V VIN = GND, Note VO = GND or VCC = 5.5V, Pins 80C286-10/883, Note 4 80C286-12/883, Note 4
Input Sustaining Current LOW Input Sustaining Current HIGH Input Sustaining Current on BUSY and ERROR Pins Output Leakage CurrentActive Power Supply Current Standby Power Supply Current NOTES:
2. IBHL should be measured after lowering VIN to GND and then raising 1.0V on the following pins: IBHH should be measured after raising VIN to VCC and then lowering 3.0V on the following pins: ICCSB should be tested with the clock stopped in phase two of the processor clock cycle. VIN = VCC or GND, VCC = 5.5V, outputs unloaded. 5. ICCOP measured at 10MHz for the 80C286-10/883 and 12.5MHz for the 80C286-12/883. VIN or 0.4V, VCC = 5.5V, outputs unloaded. 6. ISH should be measured after raising VIN to VCC and then lowering 0V on pins 53 and 54.