The 'ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Buffered common clock Buffered, asynchronous Master Reset See 'ABT377 for clock enable version See 'ABT373 for transparent latch version See 'ABT374 for TRI-STATE � version Output sink capability of 48 mA, source capability 24 mA Guaranteed latchup protection High impedance glitch free bus loading during entire power up and power down cycle Non-destructive hot insertion capability Disable time less than enable time to avoid bus contention Standard Microcircuit Drawing (SMD) 5962-9321701Features
Military W20A E20A Package Number 20-Lead Ceramic Dual-In-Line 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Package DescriptionTRI-STATE is a registered trademark of National Semiconductor Corporation.
Description Data Inputs Master Reset (Active LOW) Clock Pulse Input (Active Rising Edge) Data Outputs
H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady state I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial N = LOW-to-HIGH clock transitionOperating Mode MR Reset (Clear) Load "1" Load L H Inputs CP X
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) +5.0 mADC Latchup Source Current (Across Comm Operating Range) Over Voltage Latchup
Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input to +5.5V (V/t) 50 mV/ns 20 mV/ns
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOS ICEX ICCH ICCL ICCT Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Short-Circuit Current Output High Leakage Current Power Supply Current Power Supply Current Maximum ICC/Input Outputs Enabled 1.5 ICCD Dynamic ICC No Load 0.3 mA mA/ MHzNote 3: For 8 bits toggling, ICCD < 0.5 mA/MHz. Note 4: Guaranteed but not tested.
Recognized LOW Signal IIN -18 mA IOH -3 mA IOH -24 mA IOL 48 mA VIN = 2.7V (Note 4) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 4) VIN = 0.0V IID 1.9 �A All Other Pins Grounded VOUT = 0.0V VOUT = VCC All Outputs HIGH All Outputs LOW VI = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCC or GND Outputs Open (Note 3) One Bit Toggling, 50% Duty Cycle