The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and CPb (or both) go HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 k pull-down resistors.Features
40% power reduction of the 100151 2000V ESD protection Pin/function compatible with 100151 Voltage compensated operating range: -5.7V n Standard Microcircuit Drawing (SMD) 5962-9457901
Description Common Clock Inputs Asynchronous Master Reset Input Data Outputs Complementary Data Outputs
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care t = Time before CP positive transition t+1 = Time after CP positive transition N = LOW-to-HIGH transition
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Above which the useful life may be impaired to +150�C Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic to +0.5V VEE Pin Potential to Ground Pin Input Voltage (DC) VEE to +0.5V Output Current (DC Output HIGH) -50 mACase Temperature (TC) Military Supply Voltage (VEE) to -4.2V
Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
VEE to -5.7V, VCC = VCCA = GND, to +125�C Symbol VOH Parameter Output HIGH Voltage Min -1025 -1085 VOL Output LOW Voltage -1830 VOHC Output HIGH Voltage -1035 -1085 VOLC Output LOW Voltage -1610 -1555 VIH VIL IIL IIH Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current CP, MR D0�D5 CP, MR D0�D5 IEE Power Supply Current to +125�C
Note F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55�C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case condition at cold temperatures. Note 4: Screen tested 100% on each device -55�C, +25�C, and +125�C, Subgroups and 8. Note 5: Sample tested (Method 5005, Table I) on each manufactured lot -55�C, +25�C, and +125�C, Subgroups 3, 7, and 8. Note 6: Guaranteed by applying specified input condition and testing VOH/VOL.
Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VEE = -4.2V VIN = VIL (Min) VEE = -5.7V VIN = VIH (Max)