|SN54BCT573, SN74BCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Operating Voltage Range 5.5 V State-of-the-Art BiCMOS Design Significantly Reduces ICCZ Full Parallel Access for Loading
ESD Protection Exceeds JESD � 2000-V Human-Body Model � 200-V Machine Model � 1000-V Charged-Device Model (C101)
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the 'BCT573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels that were set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION
TA PDIP to 70�C SOIC � DW SOP � NS CDIP to 125�C CFP � W LCCC � FK PACKAGE Tube Tape and reel Tape and reel Tube ORDERABLE PART NUMBER SNJ54BCT573W SNJ54BCT573FK TOP-SIDE MARKING SNJ54BCT573J SNJ54BCT573W
SNJ54BCT573FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.FUNCTION TABLE (each latch) INPUTS OE LE OUTPUT Q0 Z
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC. 7 V Input voltage range, VI (see Note 7 V Voltage range applied to any output in the disabled or power-off state, VO. 5.5 V Voltage range applied to any output in the high state, VO. V to VCC Input clamp current, IIK (VI �30 mA Current into any output in the low state: 128 mA Package thermal impedance, JA (see Note 2): DW package. 58�C/W N package. 69�C/W NS package. 60�C/W Storage temperature range, Tstg. to 150�C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54BCT573 MIN VCC VIH VIL IIK IOH IOL Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current NOM 5 MAX 5.5 SN74BCT573 MIN NOM 5 MAX 5.5 UNIT V mA
TA Operating free-air temperature �C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
Co VCC V, 7.5 All typical values are at VCC = 25�C. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC = 25�C MIN tw tsu th Pulse duration, LE high Setup time, data before LE Hold time, data after 1 4 MAX SN54BCT573 MIN 2.5 4 MAX SN74BCT573 MIN 1 4 MAX ns UNIT