5962-9761901QCA Datasheet

ti SN54LVC86A, Quadruple 2-INPUT Exclusive-OR GATEs


Features, Applications

Operate From 3.6 V Inputs Accept Voltages 5.5 V Max tpd 3.3 V Typical VOLP (Output Ground Bounce) V at VCC = 25�C Typical VOHV (Output VOH Undershoot) V at VCC = 25�C

JESD 17 ESD Protection Exceeds JESD - 2000-V Human-Body Model - 200-V Machine Model - 1000-V Charged-Device Model (C101)

The SN54LVC86A quadruple 2-input exclusive- OR gate is designed for to 3.6-V VCC operation, and the SN74LVC86A quadruple 2-input exclusive - OR gate is designed for to 3.6-V VCC operation. The 'LVC86A devices perform the Boolean function AB in positive logic. ORDERING INFORMATION

TA PACKAGE QFN - RGY Reel of 1000 Tube of 50 SOIC to 85�C SOP - NS SSOP - DB Reel of 2500 Reel of 250 Reel of 2000 Reel of 2000 Tube of 90 TSSOP - PW CDIP to 125�C CFP - W LCCC - FK Reel of 2000 Reel of 250 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER LC86A LVC86A TOP-SIDE MARKING LC86A

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

On products compliant to MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

A common application as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output. Inputs can be driven from either or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.


An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.

These five equivalent exclusive-OR symbols are valid for an SN74LVC86A gate in positive logic; negation may be shown at any two ports. LOGIC-IDENTITY ELEMENT = EVEN-PARITY ELEMENT 2k ODD-PARITY ELEMENT + 1

The output is active (low) if all inputs stand at the same logic level (i.e., A = B).
The output is active (low) if an even number of inputs (i.e., or 2) are active.
The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC. 6.5 V Input voltage range, VI (see Note 6.5 V Output voltage range, VO (see Notes 1 and V to VCC 0.5 V Input clamp current, IIK (VI -50 mA Output clamp current, IOK (VO -50 mA Continuous output current, IO. �50 mA Continuous current through VCC or GND. �100 mA Package thermal impedance, JA (see Note 3): D package. 86�C/W (see Note 3): DB package. 96�C/W (see Note 3): NS package. 76�C/W (see Note 3): PW package. 113�C/W (see Note 4): RGY package. 47�C/W Storage temperature range, Tstg. to 150�C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5.

SN54LVC86A MIN Operating VCC Supply voltage Data retention only VCC 1.95 V VCC 2.7 V VCC 3.6 V VCC 1.95 V VIL VI VO Low-level input voltage Input voltage Output voltage VCC 1.65 V VCC 2.3 V VCC 2.7 V VCC 3 V VCC 1.65 V VCC 2.3 V VCC 2.7 V VCC 3 V VCC 2.7 V VCC 3.6 V MAX 3.6 SN74LVC86A MIN VCC 0.8 5.5 VCC ns/V mA MAX 3.6 V UNIT

TA Operating free-air temperature �C NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.



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