HomedatasheetCAT24C082JI-45TE13

CAT24C082JI-45TE13 Datasheet

1-kb, 2-kb, 4-kb, 8-Kb and 16-kb CMOS Serial Eeprom
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Features, Applications
FEATURES

Supports Standard and Fast I2C Protocol 5.5 V Supply Voltage Range 16-Byte Page Write Buffer Hardware Write Protection for entire memory Schmitt Triggers and Noise Suppression Filters

The CAT24C01/02/04/08/16 are 4-Kb, 8-Kb and 16-Kb respectively CMOS Serial EEPROM devices organized internally as 8/16/32/64 and 128 pages respectively of 16 bytes each. All devices support both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. Data is written by providing a starting address, then loading to 16 contiguous bytes into a Page Write Buffer, and then writing all data to non-volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. External address pins make it possible to address up to eight or CAT24C02, four CAT24C04, two CAT24C08 and one CAT24C16 device on the same bus.

Low power CMOS technology 1,000,000 program/erase cycles 100 year data retention Industrial temperature range RoHS-compliant 8-lead PDIP, SOIC, MSOP

For the location of Pin 1, please consult the corresponding package drawing.

A1, A2 SDA SCL WP VCC VSS NC Device Address Inputs Serial Data Input/Output Serial Clock Input Write Protect Input Power Supply Ground No Connect

* Catalyst carries the I2C protocol under a license from the Philips Corporation.
2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

ABSOLUTE MAXIMUM RATINGS(1) Storage Temperature Voltage on Any Pin with Respect to Ground(2) RELIABILITY CHARACTERISTICS(3) Symbol NEND(4) TDR Parameter Endurance Data Retention Min 1,000,000 100 Units Program/ Erase Cycles Years +6.5 V

D.C. OPERATING CHARACTERISTICS VCC to 85�C, unless otherwise specified. Symbol ICCR ICCW ISB IL VIL VIH VOL1 VOL2 Parameter Read Current Write Current Standby Current I/O Pin Leakage Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage VCC 2.5 V, IOL 3.0 mA VCC 2.5 V, IOL 1.0 mA Test Conditions Read, fSCL = 400 kHz Write, fSCL = 400 kHz All I/O Pins at GND or VCC Pin at GND or VCC -0.5 Min Max VCC x 0.3 Units mA

PIN IMPEDANCE CHARACTERISTICS VCC to 85�C, unless otherwise specified. Symbol CIN(3) IWP(5) Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Current Conditions VIN 0 V VIN 0 V VIN < VIH, VCC 5.5 V VIN < VIH, VCC 3.3 V VIN < VIH, VCC 1.8 V VIN > VIH

Note: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than V or higher than VCC 0.5 V. During transitions, the voltage on any pin may undershoot to no less than V or overshoot to no more than VCC 1.5 V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode, VCC 25�C (5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer 0.5 x VCC), the strong pull-down reverts to a weak current source.

2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

A.C. CHARACTERISTICS(1) VCC to 85�C. Standard Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF(2) tSU:STO tBUF tAA tDH Ti(2) tSU:WP tHD:WP tWR tPU(2, 3)

Note: (1) Test conditions according to "A.C. Test Conditions" table. (2) Tested initially and after a design or process change that affects this parameter. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.

Parameter Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to Data Out Valid Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time WP Hold Time Write Cycle Time Power-up to Ready Mode

A.C. TEST CONDITIONS Input Levels Input Rise and Fall Times Input Reference Levels Output Reference Levels Output Load 0.2 x VCC 0.8 x VCC

2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

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