HomedatasheetCAT24WC128PA-1.8TE13

CAT24WC128PA-1.8TE13 Datasheet

Serial CMOS EePROM, Full Array Write Protect, 128Kb
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Description

Features, Applications

1MHz I2C Bus Compatible* to 6 Volt Operation s Low Power CMOS Technology s 64-Byte Page Write Buffer s Self-Timed Write Cycle with Auto-Clear s Commercial, Industrial and Automotive s Write Protect Feature

s 100,000 Program/Erase Cycles s 100 Year Data Retention s 8-Pin DIP, 8-Pin SOIC or 14-pin TSSOP
DESCRIPTION

The a 128K-bit Serial CMOS E2PROM internally organized as 16384 words of 8 bits each. Catalyst's advanced CMOS technology substantially reduces device power requirements. The CAT24WC128 features a 64-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP, 8-pin SOIC or 14-pin TSSOP packages.

Pin Name SDA SCL WP VCC VSS Function Serial Data/Address Serial Clock Write Protect to +6V Power Supply

SCL STATE COUNTERS HIGH VOLTAGE/ TIMING CONTROL DATA IN STORAGE
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
1999 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

Temperature Under Bias................. to +125�C Storage Temperature....................... to +150�C Voltage on Any Pin with Respect �2.0V to +VCC + 2.0V VCC with Respect to Ground............... to +7.0V Package Power Dissipation Capability (Ta 25�C)................................... 1.0W Lead Soldering Temperature (10 secs)............ 300�C Output Short Circuit Current(2)........................ 100mA RELIABILITY CHARACTERISTICS Symbol NEND TDR VZAP

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

Parameter Endurance Data Retention ESD Susceptibility Latch-up

Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS VCC to +6.0V, unless otherwise specified. Limits Symbol ICC2 ISB(5) ILI ILO VIL VIH VOL1 VOL2 Parameter Power Supply Current - Read Power Supply Current - Write Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = +3.0V) Output Low Voltage (VCC +1.8V) �1 VCC x 0.7 Min. Typ. Max. VCC x 0.3 VCC Units mA �A IOL 3.0 mA IOL 1.5 mA Test Conditions fSCL = 100 KHz VCC=5V fSCL = 100 KHz VCC=5V VIN = GND or VCC VCC=5V VIN = GND to VCC VOUT = GND to VCC

CAPACITANCE = 1.0 MHz, VCC = 5V Symbol CI/O(3) CIN(3) Test Input/Output Capacitance (SDA) Input Capacitance (SCL, WP) Max. 8 6 Units pF Conditions VI/O = 0V VIN = 0V

Note: (1) The minimum DC input voltage is �0.5V. During transitions, inputs may undershoot to �2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses mA on address and data pins from �1V to VCC +1V. (5) Standby current (ISB �A (<900 nA).

A.C. CHARACTERISTICS VCC to +6V, unless otherwise specified Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits Symbol Parameter

FSCL tAA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF(1) tSU:STO tDH tWR

Clock Frequency SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Write Cycle Time

Power-Up Timing (1)(2) Symbol tPUR tPUW Parameter Power-Up to Read Operation Power-Up to Write Operation Max. 1 Units ms

Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

The CAT24WC128 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus be a transmitter and any device receiving data be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC128 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated.


Features

Parameters

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Manufacturer information

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