s 5 MHz SPI Compatible to 6.0 Volt Operation s Hardware and Software Protection s Zero Standby Current s Low Power CMOS Technology s SPI Modes &1,1)* s Commercial, Industrial and Automotive
s 100,000 Program/Erase Cycles s 100 Year Data Retention s Self-Timed Write Cycle s 8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOPs 64-Byte Page Write Buffer s Block Write Protection
The a 128K/256K-Bit SPI Serial CMOS EEPROM internally organized as 16Kx8/32Kx8 bits. Catalyst's advanced CMOS Technology substantially reduces device power requirements. The CAT25C128/256 features a 64-byte page write buffer. The device operates via the SPI bus serial interface and is enabled through a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C128/256 is designed with software and hardware write protection features including Block Lock protection. The device is available in 8-pin DIP, 8-pin SOIC, 16-pin SOIC, 14-pin TSSOP and 20-pin TSSOP packages.SOIC Package (S16, V)** TSSOP Package (U20, Y)**
I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC
Pin Name SO SCK WP VCC VSS CS SI HOLD NC Function Serial data Output Serial Clock Write Protect to +6.0V Power Supply Ground Chip Select Serial Data Input Suspends Serial Input No ConnectDATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL STATUS REGISTER
2003 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Temperature Under Bias................. to +125�C Storage Temperature....................... to +150�C Voltage on any Pin with Respect �2.0V to +VCC +2.0V VCC with Respect to VSS................................ to +7.0V Package Power Dissipation Capability (Ta 25�C)................................... 1.0W Lead Soldering Temperature (10 secs)............ 300�C Output Short Circuit 100 mA RELIABILITY CHARACTERISTICS Symbol NEND
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS VCC to +6.0V, unless otherwise specified. Limits Symbol ICC1 ICC2 ISB ILI ILO VOL2 VOH2 Parameter Power Supply Current (Operating Write) Power Supply Current (Operating Read) Power Supply Current (Standby) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VCC-0.2 VCC x 0.7 Min. Typ. Max. VCC x 0.3 VCC 0.5 0.4 Units �A 4.5VVCC<5.5V IOL = 3.0mA IOH -1.6mA 1.8VVCC<2.7V IOL = 150�A IOH = -100�A VOUT 0V to VCC, = 0V Test Conditions VCC @ 10MHz SO=open; CS=Vss VCC = 5.0V FCLK CS = VCC VIN = VSS or VCC
Note: (1) The minimum DC input voltage is �0.5V. During transitions, inputs may undershoot to �2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses mA on address and data pins from �1V to VCC +1V.
Applicable over recommended operating range from TA=25�C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD)
A.C. CHARACTERISTICS (CAT25C128) Limits Vcc= 1.8V-6.0V SYMBOL PARAMETER tSU tH tWH tWL fSCK tLZ tRI(1) tFI
Data Setup Time Data Hold Time SCK High Time SCK Low Time Clock Frequency HOLD to Output Low Z Input Rise Time Input Fall Time HOLD Setup Time HOLD Hold Time Write Cycle Time Output Valid from Clock Low Output Hold Time Output Disable Time HOLD to Output High Z CS High Time CS Setup Time CS Hold Time WP Setup Time WP Hold Time
NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter.