|s Fast Read Access Times: ns s Low Power CMOS Dissipation: s Automatic Page Write Operation:
�On-Chip Address and Data Latches �Self-Timed Write Cycle with Auto-Clear
s Hardware and Software Write Protection s 100,000 Program/Erase Cycles s 100 Year Data Retention s Commercial, Industrial and AutomotiveDESCRIPTION
The is a fast,low power, 5V-only CMOS parallel EEPROM organized 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28C512/513 features hardware and software write protection. The CAT28C512/513 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 32-pin DIP, PLCC, 32-pin TSOP and 40-pin TSOP packages.
ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 8 E2PROM ARRAY 128 BYTE PAGE REGISTERCONTROL I/O BUFFERS TIMER DATA POLLING AND TOGGLE BIT COLUMN DECODER
2001 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
PIN FUNCTIONS Pin Name CE OE Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Pin Name WE VCC VSS NC Function Write Enable 5V Supply Ground No Connect
Temperature Under Bias................. to +125�C Storage Temperature....................... to +150�C Voltage on Any Pin with Respect �2.0V to +VCC + 2.0V VCC with Respect to Ground............... to +7.0V Package Power Dissipation Capability (Ta 25�C)................................... 1.0W Lead Soldering Temperature (10 secs)............ 300�C Output Short Circuit 100 mA RELIABILITY CHARACTERISTICS Symbol VZAP(1) ILTH(1)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min Max.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS VCC 5V �10%, unless otherwise specified. Limits Symbol ICC ICCC(5) ISB ISBC(6) ILI ILO VIH(6) VIL(5) VOH VOL VWI Parameter VCC Current (Operating, TTL) VCC Current (Operating, CMOS) VCC Current (Standby, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Write Inhibit Voltage Min Typ Max. VCC +0.3 0.8 Units mA �A IOH = �400�A IOL = 2.1mA Test Conditions OE = VIL, f=6MHz All I/O's Open OE = VILC, f=6MHz All I/O's Open CE = VIH, All I/O's Open CE = VIHC, All I/O's Open VIN = GND to VCC VOUT = GND to VCC, CE = VIH
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is �0.5V. During transitions, inputs may undershoot to �2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses 100mA on address and data pins from �1V to VCC +1V. (5) VILC +0.3V. (6) VIHC = VCC �0.3V to VCC +0.3V.