s Fast read access times: s Commercial, industrial and automotive
� On-chip address and data latches � Self-timed write cycle with auto-clear
s CMOS and TTL compatible I/O s Hardware and software write protection
The is a fast, low power, 5V-only CMOS parallel EEPROM organized 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling, a RDY/BUSY pin and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28C65B features hardware and software write protection. The CAT28C65B is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDECapproved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32pin PLCC packages.
A5�A12 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 8 E2PROM ARRAY 32 BYTE PAGE REGISTERCONTROL LOGIC I/O BUFFERS TIMER DATA POLLING, TOGGLE BIT & RDY/BUSY LOGIC COLUMN DECODER
2001 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Pin Name CE OE RDY/BSY Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Ready/Busy Status Pin Name WE VCC VSS NC Function Write Enable 5 V Supply Ground No Connect
Temperature Under Bias................. to +125�C Storage Temperature....................... to +150�C Voltage on Any Pin with Respect �2.0V to +VCC + 2.0V VCC with Respect to Ground............... to +7.0V Package Power Dissipation Capability (Ta 25�C)................................... 1.0W Lead Soldering Temperature (10 secs)............ 300�C Output Short Circuit 100 mA RELIABILITY CHARACTERISTICS Symbol VZAP(1) ILTH(1)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. Max.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby, and Write Inhibit Read and Write Inhibit H OE I/O DOUT DIN High-Z Power ACTIVE STANDBY ACTIVE
CAPACITANCE = 1.0 MHZ, VCC = 5V Symbol Test Max. CI/O(1) CIN(1) Input/Output Capacitance Input Capacitance 10 6
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is �0.5V. During transitions, inputs may undershoot to �2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses 100mA on address and data pins from �1V to VCC +1V.