|2 Megabit CMOS Boot Block Flash Memory FEATURES
s Fast Read Access Time: ns s On-Chip Address and Data Latches s Blocked Architecture: s Electronic Signature
One 16-KB Protected Boot Block Top or Bottom Locations Two 8-KB Parameter Blocks One 96-KB Main Block One 128-KB Main Block
s Hardware Data Protection s Automated Program and Erase Algorithms s Automatic Power Savings Feature s Low Power CMOS Operation s 12.0Vs High Speed Programming s Commercial, Industrial and Automotive Tem-
The is a high speed X 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after sale code updates. The CAT28F002 has a blocked architecture with one 16 KB Boot Block, two 8 KB Parameter Blocks, one 96 KB Main Block and one 128 KB Main Block. The Boot Block section can be at the top or bottom of the memory map. The Boot Block section includes a reprogramming write lock out feature to guarantee data integrity. It is designed to contain secure code which will bring up the system minimally and download code to other locations of CAT28F002. The CAT28F002 is designed with a signature mode which allows the user to identify the IC manufacturer and device type. The CAT28F002 is also designed with onChip Address Latches, Data Latches, Programming and Erase Algorithms. A deep power-down mode lowers the total Vcc power consumption 1�w typical. The CAT28F002 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 40-pin TSOP and 40-pin PDIP packages.
ADDRESS COUNTER WRITE STATE MACHINE RP WE COMMAND REGISTER PROGRAM VOLTAGE SWITCH CE, OE LOGIC ERASE VOLTAGE SWITCH
Y-GATING Y-DECODER 16K-BYTE BOOT BLOCK 8K-BYTE PARAMETER BLOCK 8K-BYTE PARAMETER BLOCK 96K-BYTE MAIN BLOCK 128K-BYTE MAIN BLOCK1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Pin Name OE WE VCC VSS VPP RP DU Input Type Input I/O Input Function Address Inputs for memory addressing Data Input/Output Chip Enable Output Enable Write Enable Voltage Supply Ground Program/Erase Voltage Supply Power Down Do Not Use
Temperature Under Bias................... to +95�C Storage Temperature....................... to +150�C Voltage on Any Pin with Respect �2.0V to +VCC + 2.0V Voltage on Pin A9 with Respect to +13.5V VPP with Respect to Ground during to +14.0V VCC with Respect to +7.0V Package Power Dissipation Capability (TA 1.0 W Lead Soldering Temperature (10 secs)............ 300�C Output Short Circuit 100 mA
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
CAPACITANCE = 1.0 MHz Limits Symbol COUT(3) CVPP(3) Test Input Pin Capacitance Output Pin Capacitance VPP Supply Capacitance Min Max. 12 25 Units pF Conditions VIN = 0V VOUT = 0V VPP = 0V
Note: (1) The minimum DC input voltage is �0.5V. During transitions, inputs may undershoot to �2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses mA on address and data pins from �1V to VCC +1V.